Laser Annealing Technology and Device Integration Challenges

Abstract

We have shown impacts of halo and deep source/drain (S/D) junction on the performance of devices that were fabricated by non-melt laser spike annealing (LSA). By optimizing both profiles, we achieved 10%-better performance and reduced hot carrier degradation compared to those by the conventional LSA that have only the optimized gate-S/D overlap structure. Gate pre-annealing by laser thermal process (LTP) was also investigated in conjunction with LSA S/D activation to effectively suppress poly-Si gate depletion while achieving highly activated ultra-shallow junctions in S/D, leading to improved transistor performance. Ioff was reduced more than one order of magnitude compared with conventional spike RTA devices