2018 IEEE International Conference on Semiconductor Electronics (ICSE)最新文献

Optical Properties of Multilayer Porous Silicon with Different Fabrication Conditions for Application along Telecom Band 不同制备条件下多层多孔硅在电信波段应用的光学特性

2018 IEEE International Conference on Semiconductor Electronics (ICSE) Pub Date : 2018-10-03 DOI: 10.1109/SMELEC.2018.8481281

Ahmad Afif Safwan Mohd Radzi, M. Rusop, S. Abdullah

引用次数: 2

Synthesis of ZnO nanoflakes by 1064 nm Nd:YAG pulsed laser deposition in a horizontal tube furnace 1064 nm Nd:YAG脉冲激光沉积法制备ZnO纳米片

2018 IEEE International Conference on Semiconductor Electronics (ICSE) Pub Date : 2018-08-01 DOI: 10.1109/SMELEC.2018.8481292

Kong Eng Ng, T. Y. Tiong, M. Mohamed, W. Chang, C. Dee, B. Majlis

引用次数: 0

Facile Synthesis of N-doped ZnO Nanorod Arrays: Towards Enhancing the UV-sensing Performance n掺杂ZnO纳米棒阵列的简易合成:增强紫外传感性能

2018 IEEE International Conference on Semiconductor Electronics (ICSE) Pub Date : 2018-08-01 DOI: 10.1109/SMELEC.2018.8481321

A. S. Ismail, M. H. Mamat, M. F. Malek, N. Azhar, N. H. Sulimai, R. A. Rani, A. Zoolfakar, M. Rusop

引用次数: 0

Design and simulation of tapered optical fiber by enhancing the evanescent field region for sensing application 基于增强倏逝场区的锥形光纤的设计与仿真

2018 IEEE International Conference on Semiconductor Electronics (ICSE) Pub Date : 2018-08-01 DOI: 10.1109/SMELEC.2018.8481202

Nurulhani Diana Rashid, D. Berhanuddin, M. Mahdi, B. Majlis, A. Zain

引用次数: 1

Design of Phase Frequency Detector (PFD),Charge Pump (CP) and Programmable Frequency Divider for PLL in 0.18um CMOS Technology 0.18um CMOS技术锁相环相频检测器(PFD)、电荷泵(CP)和可编程分频器的设计

2018 IEEE International Conference on Semiconductor Electronics (ICSE) Pub Date : 2018-08-01 DOI: 10.1109/SMELEC.2018.8481309

A. A. Ahmad, S. M. Md Ali, N. Kamal, Siti Raudzah Abdul Rahman, M. Othman

引用次数: 8

Characterization of SOI Film Thickness, Oxide Thickness and Charges with C-V Measurement 用C-V测量表征SOI薄膜厚度、氧化物厚度和电荷

2018 IEEE International Conference on Semiconductor Electronics (ICSE) Pub Date : 2018-08-01 DOI: 10.1109/SMELEC.2018.8481314

K. Joseph, T. C. Lik, Niew Soon Huat

引用次数: 0

First Principle Study of Graphene-Carbon Nanotubes Hybrid (GCH) Structure for Advanced Nanoelectronics Devices 先进纳米电子器件中石墨烯-碳纳米管杂化结构的第一性原理研究

2018 IEEE International Conference on Semiconductor Electronics (ICSE) Pub Date : 2018-08-01 DOI: 10.1109/SMELEC.2018.8481215

L. Theng, I. Yahya, M. A. Mohamed, Mahamad Fariz Mohamad Taib

{"title":"First Principle Study of Graphene-Carbon Nanotubes Hybrid (GCH) Structure for Advanced Nanoelectronics Devices","authors":"L. Theng, I. Yahya, M. A. Mohamed, Mahamad Fariz Mohamad Taib","doi":"10.1109/SMELEC.2018.8481215","DOIUrl":"https://doi.org/10.1109/SMELEC.2018.8481215","url":null,"abstract":"Although graphene and carbon nanotubes (CNT) exhibit remarkable electronic and mechanical properties, these two carbon allotropes face limitations due to their nanoscale size. The combination of graphene and CNT are suggested to overcome the problem of bundling and stacking in CNT and graphene which limit their performance. First principle study is carried out on the electronic properties of graphene-carbon nanotubes hybrid (GCH) structure using BIOVIA Material Studio software. Density Functional Theory (DFT) is used to calculate its band structure and density of states. The results show that when semiconducting CNT combine with graphene, its band gap is reduced compare to the pristine CNT. However, when metallic CNT is combine with graphene, the changes in band gap is depend on CNT's chirality. Chiral CNT will decrease the band gap of GCH, zigzag CNT causes not much changes in its GCH, while armchair CNT will increase the band gap of its GCH. Therefore, the result shows that it is possible to tune the band gap of GCH by combining graphene sheet with different type of CNT depending on our needs.","PeriodicalId":110608,"journal":{"name":"2018 IEEE International Conference on Semiconductor Electronics (ICSE)","volume":"143 9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126016670","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Activation energy of thermal oxidation germanium oxide on germanium substrates 锗基热氧化氧化锗的活化能

2018 IEEE International Conference on Semiconductor Electronics (ICSE) Pub Date : 2018-08-01 DOI: 10.1109/SMELEC.2018.8481204

N. A. A. Halim, S. K. Sahari, A. A. Hamzah, B. Majlis, S. Marini, L. Hasanah, M. Kashif

引用次数: 1

Integration Design of Wide-Dynamic-Range MEMS Magnetometer and Oscillator 宽动态范围MEMS磁强计与振荡器的集成设计

2018 IEEE International Conference on Semiconductor Electronics (ICSE) Pub Date : 2018-08-01 DOI: 10.1109/SMELEC.2018.8481282

Chao Song, K. Wen

引用次数: 4

Tunable Steep Slope MoS2 Transistor 可调陡坡MoS2晶体管

2018 IEEE International Conference on Semiconductor Electronics (ICSE) Pub Date : 2018-08-01 DOI: 10.1109/SMELEC.2018.8481317

N. Bhat

{"title":"Tunable Steep Slope MoS2 Transistor","authors":"N. Bhat","doi":"10.1109/SMELEC.2018.8481317","DOIUrl":"https://doi.org/10.1109/SMELEC.2018.8481317","url":null,"abstract":"The CMOS scaling is now facing serious fundamental and technological challenges resulting in diminishing performance and economic returns. The concurrent reduction in power consumption, an important aspect of scaling, has become difficult, because of the inability to reduce supply voltage below 1 V. This is primarily because the fundamental nature of charge transport governed by Boltzmann's statistics restricts the Sub-threshold Swing (SS, abruptness between OFF to ON transitions) of FETs to the thermionic limit of 60 mV/dec at room temperature. Hence, as we cram in more transistors into the same footprint, energy dissipation and heat management have become fundamental bottlenecks. Clearly, the road ahead needs breakthroughs in new materials and device design. In this talk, I will present a new device architecture to beat the Boltzmann limit. We demonstrate, for the first time, sub-thermionic transport through tunable Schottky contacts in dual gated MoS2 FETs. two device configurations the gate tunable thermionic tunnel transistor (GT3) and dynamic Vt and adaptable transport transistor (DVAT) are expounded. The GT3 transistor has the flexibility to operate either in the sub-thermionic tunnel regime, yielding steep SS<60 mV/dec OR thermionic high mobility regime. Combining the best of both tunnelling and thermionic regimes in the same operation cycle, the DVAT transistor, the closest to an ‘ideal transistor’, registers SS~29 mV/dec (3 dec) AND high mobility (100 cm2V-1s-1). This work is envisioned to pave a new path in the development of sub-thermionic, high performance FETs operating in the sub-0.5 V ‘green computing’ regime.","PeriodicalId":110608,"journal":{"name":"2018 IEEE International Conference on Semiconductor Electronics (ICSE)","volume":"179 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116173303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1