Design of Phase Frequency Detector (PFD),Charge Pump (CP) and Programmable Frequency Divider for PLL in 0.18um CMOS Technology

Abstract

In this paper, a Phase Frequency Detector (PFD) Charge Pump (CP) and programmable frequency divider Phase Locked Loop (PLL) for Bluetooth Low Energy (BLE) are presented. It is implemented using 180nm CMOS technology. The programmable frequency divider consists of Dual Modulus Prescaler divide by 15/16, 7-Bit Programmable Counter (P), and 6-Bit Swallow Counter (S). The divider will operate between 2.4–2.48 GHz frequency with 40 channels frequency hopping. The design has been simulated with 1.8 Vdd and consumed 3.51mW power.