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Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)最新文献

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Substrate noise in mixed signal circuits: two case studies [CMOS] 混合信号电路中的衬底噪声:两个案例研究[CMOS]
Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372) Pub Date : 1998-09-13 DOI: 10.1109/ASIC.1998.722799
David G. England
{"title":"Substrate noise in mixed signal circuits: two case studies [CMOS]","authors":"David G. England","doi":"10.1109/ASIC.1998.722799","DOIUrl":"https://doi.org/10.1109/ASIC.1998.722799","url":null,"abstract":"There are many noise sources in integrated circuits that can affect sensitive analog nodes. The role of substrate noise is often glossed over since the designer 'knows' that guard rings and separation of the analog section from digital circuits should take care of the noise. However, with smaller geometries now being the norm, it is increasingly difficult to isolate analog nodes from noise induced on the substrate. Also, package economics have introduced other factors that weigh heavily against the analog designer. This paper explores two cases of noise induced on the substrate affecting operation of analog circuits.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114224116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A flexible pipelined image processor 一个灵活的流水线图像处理器
Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372) Pub Date : 1998-09-13 DOI: 10.1109/ASIC.1998.723026
M. Kelly, K. Hsu
{"title":"A flexible pipelined image processor","authors":"M. Kelly, K. Hsu","doi":"10.1109/ASIC.1998.723026","DOIUrl":"https://doi.org/10.1109/ASIC.1998.723026","url":null,"abstract":"This paper describes the design of a flexible, pipelined general image processor (GIP) using VHDL to model the top level design and functional blocks consisting of histogram modification, convolution, halftone, error diffusion, and threshold. The GIP was simulated to have a processing speed of 70 Mpixels/second. A four pixel wide image data path is used so a clock of 17.5 MHz can be used. Mentor Graphics tool suites were used to perform the simulation and synthesis of the design. The total number of gates in 1.2 /spl mu/m CMOS gate array was estimated to be 236 K gates, less than 1 million transistors.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122898190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A new current-mode sense amplifier for low-voltage low-power SRAM 一种新型低压低功耗SRAM电流模式检测放大器
Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372) Pub Date : 1998-09-13 DOI: 10.1109/ASIC.1998.722884
Jinn-Shyan Wang, Hong-Yu Lee
{"title":"A new current-mode sense amplifier for low-voltage low-power SRAM","authors":"Jinn-Shyan Wang, Hong-Yu Lee","doi":"10.1109/ASIC.1998.722884","DOIUrl":"https://doi.org/10.1109/ASIC.1998.722884","url":null,"abstract":"A new current-mode sense amplifier is proposed and it can be used in the design of a low-voltage low-power SRAM for ASIC applications. In the new current-mode sense amplifier a modified current-conveyor is used to prevent the pattern dependent problem which is overlooked in the previous designs. Simulation results show the conventional circuits will fail and the new circuit can work if V/sub DD/=1.5 V and an industrial 0.35 /spl mu/m CMOS technology is used. Power consumption of the new circuit with V/sub DD/=1.5 V is only 6%/spl sim/39% of the conventional circuits running at V/sub DD/=2.0 V. A 128/spl times/8 SRAM using the new circuit for V/sub DD/=2.0 V in a 0.6 /spl mu/m CMOS technology is also designed and successfully applied in an 8-bit low-power microcontroller.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"291 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115955876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
Current-testable high-frequency CMOS operational amplifiers 电流可测试的高频CMOS运算放大器
Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372) Pub Date : 1998-09-13 DOI: 10.1109/ASIC.1998.722810
J. Velasco-Medina, S. Mir, M. Nicolaidis
{"title":"Current-testable high-frequency CMOS operational amplifiers","authors":"J. Velasco-Medina, S. Mir, M. Nicolaidis","doi":"10.1109/ASIC.1998.722810","DOIUrl":"https://doi.org/10.1109/ASIC.1998.722810","url":null,"abstract":"A new test approach for high-frequency operational amplifiers based on current injection is presented in this paper. Current-based test stimuli allow detection of some faults which are difficult to detect or are untestable when conventional voltage-based test stimuli are used. In addition, the selection of test stimuli is simpler since faulty behaviours are observable in the whole frequency band with current injection. An example of a current-testable operational amplifier has been designed, and the small test circuitry required for current injection has a negligible impact on circuit performance.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129402593","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Image sensors in industrial/machine vision applications 工业/机器视觉应用中的图像传感器
Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372) Pub Date : 1998-09-13 DOI: 10.1109/ASIC.1998.723045
J. Vieth
{"title":"Image sensors in industrial/machine vision applications","authors":"J. Vieth","doi":"10.1109/ASIC.1998.723045","DOIUrl":"https://doi.org/10.1109/ASIC.1998.723045","url":null,"abstract":"This tutorial presents the basic characteristics of industrial applications of solid state image sensors. The contents of this paper are an abbreviated version of the tutorial presented at the ASIC'98 Conference. Image sensor technology requirements are described. Various system architectures are discussed. Important system criteria for industrial imaging are examined. The tutorial concludes with suggested vision system benefits from future developments in VLSI technology.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128196115","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design of a slew rate controlled output buffer 摆率控制输出缓冲器的设计
Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372) Pub Date : 1998-09-13 DOI: 10.1109/ASIC.1998.722821
Fernando Quiles García, P. Coll., D. Anvergne
{"title":"Design of a slew rate controlled output buffer","authors":"Fernando Quiles García, P. Coll., D. Anvergne","doi":"10.1109/ASIC.1998.722821","DOIUrl":"https://doi.org/10.1109/ASIC.1998.722821","url":null,"abstract":"Due to the wide range of IC operating conditions, designing I/O drivers does not constitute a trivial task. Output ringing due to over-drive as well as power noise due to simultaneous switching of output drivers must be avoided. A structure of an output driver is proposed that uses capacitance feedback to control the output slew, reducing the power noise. The transition time of the resulting driver is shown to be constant over a large range of output loading conditions. A description is given of a driver implemented in a 0.8 /spl mu/m CMOS technology.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116552373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Modular realization of threshold logic gates for high performance digital signal processing applications 用于高性能数字信号处理应用的阈值逻辑门的模块化实现
Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372) Pub Date : 1998-09-13 DOI: 10.1109/ASIC.1998.722997
Y. Leblebici, F. Gurkaynak
{"title":"Modular realization of threshold logic gates for high performance digital signal processing applications","authors":"Y. Leblebici, F. Gurkaynak","doi":"10.1109/ASIC.1998.722997","DOIUrl":"https://doi.org/10.1109/ASIC.1998.722997","url":null,"abstract":"In this paper, a modular realization of capacitive threshold logic (CTL) gates is proposed, offering significant advantages in terms of silicon area and speed in certain applications. The generic CTL circuit architecture is presented, its main building blocks are introduced and the operation of the circuit is discussed. A layout design automation environment is presented for the automatic generation of mask-level layout of CTL gates, using conventional CMOS fabrication technology.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132046627","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A nonlinear integrator model used to design a robust 16-bit, 40 kSPS switched capacitor sigma-delta modulator 采用非线性积分器模型设计鲁棒的16位40 kSPS开关电容sigma-delta调制器
Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372) Pub Date : 1998-09-13 DOI: 10.1109/ASIC.1998.722805
D. McGrath, J. Tiemann, R. Gutmann
{"title":"A nonlinear integrator model used to design a robust 16-bit, 40 kSPS switched capacitor sigma-delta modulator","authors":"D. McGrath, J. Tiemann, R. Gutmann","doi":"10.1109/ASIC.1998.722805","DOIUrl":"https://doi.org/10.1109/ASIC.1998.722805","url":null,"abstract":"The design of robust high-order sigma-delta modulator circuits is difficult since linear analysis cannot be used to accurately estimate performance characteristics such as signal-to-noise ratio (SNR) and signal-to-distortion ratio (SDR). Designers rely on time-domain simulation of the modulator loop to evaluate these critical performance characteristics. A new model for a switched capacitor integrator is presented and evaluated. Accurate models of the integrators are developed from integrator circuit simulation. The model provides the speed of look-up table based modulator simulation while also providing useful input for design modification not available when using look-up table based simulation methods.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"131 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134263737","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
QPSK demodulator using the methodology of automated system-level ASIC design 采用QPSK解调的方法对系统级ASIC进行自动化设计
Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372) Pub Date : 1998-09-13 DOI: 10.1109/ASIC.1998.723017
Dae-Soon Kim, Hwak-Dong Park, Chan-Hyoung Kang
{"title":"QPSK demodulator using the methodology of automated system-level ASIC design","authors":"Dae-Soon Kim, Hwak-Dong Park, Chan-Hyoung Kang","doi":"10.1109/ASIC.1998.723017","DOIUrl":"https://doi.org/10.1109/ASIC.1998.723017","url":null,"abstract":"The design methodology and the basic features of a QPSK digital demodulator fully compliant with the DVB/DSS Recommendations are presented. The ASIC design and development process employs an \"automated system-level design scheme\" as a new system ASIC design methodology. This paper discusses the nonsynchronized sampling QPSK demodulation algorithm as an illustrative algorithm in order to demonstrate the benefits when developing such an algorithm using a system-level design scheme.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133613088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Neural ASIC controller for PWM power systems PWM电源系统的神经专用集成电路控制器
Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372) Pub Date : 1998-09-13 DOI: 10.1109/ASIC.1998.722794
A. Dinu, M. Cirstea, M. McCormick, A. Ometto, N. Rotondalle
{"title":"Neural ASIC controller for PWM power systems","authors":"A. Dinu, M. Cirstea, M. McCormick, A. Ometto, N. Rotondalle","doi":"10.1109/ASIC.1998.722794","DOIUrl":"https://doi.org/10.1109/ASIC.1998.722794","url":null,"abstract":"This paper describes an ASIC approach of a predictive current controller for VLSI-PWM inverters used in power systems. The new structure is based on FPGA implementation of neural networks providing high performance and compact hardware structure. The operation principles, architecture, design and implementation strategy are presented alongside with simulation results.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115327871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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