{"title":"Design of a slew rate controlled output buffer","authors":"Fernando Quiles García, P. Coll., D. Anvergne","doi":"10.1109/ASIC.1998.722821","DOIUrl":null,"url":null,"abstract":"Due to the wide range of IC operating conditions, designing I/O drivers does not constitute a trivial task. Output ringing due to over-drive as well as power noise due to simultaneous switching of output drivers must be avoided. A structure of an output driver is proposed that uses capacitance feedback to control the output slew, reducing the power noise. The transition time of the resulting driver is shown to be constant over a large range of output loading conditions. A description is given of a driver implemented in a 0.8 /spl mu/m CMOS technology.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"16","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASIC.1998.722821","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 16
Abstract
Due to the wide range of IC operating conditions, designing I/O drivers does not constitute a trivial task. Output ringing due to over-drive as well as power noise due to simultaneous switching of output drivers must be avoided. A structure of an output driver is proposed that uses capacitance feedback to control the output slew, reducing the power noise. The transition time of the resulting driver is shown to be constant over a large range of output loading conditions. A description is given of a driver implemented in a 0.8 /spl mu/m CMOS technology.