A flexible pipelined image processor

M. Kelly, K. Hsu
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引用次数: 1

Abstract

This paper describes the design of a flexible, pipelined general image processor (GIP) using VHDL to model the top level design and functional blocks consisting of histogram modification, convolution, halftone, error diffusion, and threshold. The GIP was simulated to have a processing speed of 70 Mpixels/second. A four pixel wide image data path is used so a clock of 17.5 MHz can be used. Mentor Graphics tool suites were used to perform the simulation and synthesis of the design. The total number of gates in 1.2 /spl mu/m CMOS gate array was estimated to be 236 K gates, less than 1 million transistors.
一个灵活的流水线图像处理器
本文描述了一种灵活的流水线通用图像处理器(GIP)的设计,使用VHDL对其顶层设计和由直方图修改、卷积、半色调、误差扩散和阈值组成的功能模块进行建模。模拟GIP的处理速度为70万像素/秒。使用四像素宽的图像数据路径,因此可以使用17.5 MHz的时钟。使用Mentor Graphics工具套件对设计进行仿真和综合。1.2 /spl mu/m CMOS栅极阵列的栅极总数估计为236 K栅极,少于100万个晶体管。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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