Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)最新文献_第7页

Incremental routing in FPGAs fpga中的增量路由

Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372) Pub Date : 1998-09-13 DOI: 10.1109/ASIC.1998.722907

J. Emmert, D. Bhatia

引用次数: 39

800 K gates of random logic in four months: discussion on design methodologies based on "IDEFIX" ASIC experience 4个月800k随机逻辑门:基于“IDEFIX”ASIC经验的设计方法探讨

Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372) Pub Date : 1998-09-13 DOI: 10.1109/ASIC.1998.722894

S. Gastaldello, G. Traverso, R. Kase

{"title":"800 K gates of random logic in four months: discussion on design methodologies based on \"IDEFIX\" ASIC experience","authors":"S. Gastaldello, G. Traverso, R. Kase","doi":"10.1109/ASIC.1998.722894","DOIUrl":"https://doi.org/10.1109/ASIC.1998.722894","url":null,"abstract":"Reusability of basic building blocks is an important and effective goal in ASIC design: it speeds up the design, it minimizes the overall bug probability, it eases documentation and maintenance of core functions. Nevertheless, this approach means also a \"black box\" management, requiring some extra efforts in the implementation phase. Alcatel and Toshiba proved a solution to cope with the lack of knowledge and control of re-used blocks. This methodology seems to be effective, especially for million gates designs in deep submicron technologies. This paper discusses a real ASIC design case, where classical issues were combined: tough schedule; large glue logic (800 K netlist gates), with high connectivity; many clock domains (65 clocks), with many interactions; 50% reuse of old building blocks, many from netlist. The proposed flow improves by shortening design time, achieving high synthesis efficiency without usage of time consuming CRWC methodology, achieving high layout efficiency bypassing time consuming (and sometimes misleading) floorplanning /hierarchical methodologies.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114247915","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Designing Real-Life Applications Using Synopsys Behavioral Compiler 使用Synopsys行为编译器设计实际应用程序

Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372) Pub Date : 1998-09-13 DOI: 10.1109/ASIC.1998.723089

V. P. Raghavan

引用次数: 0

A low distortion linear-tunable continuous-time 488 kHz fifth-order Bessel filter 低失真线性可调连续时间488 kHz五阶贝塞尔滤波器

Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372) Pub Date : 1998-09-13 DOI: 10.1109/ASIC.1998.722801

J. Egerer, T. Desel, Popken, J. Boxho, D. Macq, J. Cornil

引用次数: 6

Low power design for speech codec 语音编解码器的低功耗设计

Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372) Pub Date : 1998-09-13 DOI: 10.1109/ASIC.1998.722818

T. Okamura, Y. Kinoshita, H. Yoshida, D. Yamane

引用次数: 1

Mems/cmos Integration & Image Sensors Mems/cmos集成与图像传感器

Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372) Pub Date : 1998-09-13 DOI: 10.1109/ASIC.1998.723042

P. Lee, C. Anagnopoulis

引用次数: 1

Ultra low-voltage current mirrors and pseudo differential pairs 超低电压电流镜和伪差分对

Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372) Pub Date : 1998-09-13 DOI: 10.1109/ASIC.1998.722813

Y. Berg, T. Lande

引用次数: 10

A low noise cryogenic CMOS preamplifier for high critical temperature superconducting IR and FIR sensors 用于高温超导红外和FIR传感器的低噪声低温CMOS前置放大器

Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372) Pub Date : 1998-09-13 DOI: 10.1109/ASIC.1998.723057

G. Klisnick, Y. Hu, F. Voisin, M. Redon, A. Gaugue, A. Kreisler

引用次数: 0

Core-based Design Of Systems On A Chip 基于核心的单片系统设计

Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372) Pub Date : 1998-09-13 DOI: 10.1109/ASIC.1998.723087

J. Henkel, F. Vahid

{"title":"Core-based Design Of Systems On A Chip","authors":"J. Henkel, F. Vahid","doi":"10.1109/ASIC.1998.723087","DOIUrl":"https://doi.org/10.1109/ASIC.1998.723087","url":null,"abstract":"The growth in integration capacity allows to integrate complete systems on one single chip (SOC: systems-on-a-chip). Since traditional design tools can not keep pace with this rapid growth, so-called core-based design methodologies become more and more important for today’s system designer. In this context, a core can be a microprocessor, a controller, a multimedia application, etc. Distinguished are often three levels of cores: soft, firm and hard cores. Whereas a soft core is a non-synthesized, often technology independent HDL description of a circuit, a hard core is readily synthesized and verified. A f i core is somewhere between and owns some peculiarities of soft cores and some of hard cores. By composing a system of a mixture of soft, f i and hard cores, the system designer is enabled to achieve the best compromise between parameterization, customization and re-usability. As a result, the time-to-market as well as system costs can be drastically reduced. In this four-hour tutorial the authors will give an overview of core-based design methodologies while mainly focussing on the following decisive design aspects: Integration of cores on a chip: a) Integration is the process of adapting various cores to each other according to given design goals and afterwards synthesizing these cores (if applicable) in order to obtain a singlechip-solution. Among other steps, this procedure involves the selection of appropriate interfaces since this matter is directly related to design goalslconstraints like system performance, total chip area, system power dissipation, system costs, etc. Whereas intra-chip interfaces (between the SOC and the environment, for example), is limited to standard interfaces. The tutorial will give some examples for the integration procedure with emphasize on interface selection for different design goalskonstraints. Frank Vahid Department of Computer Science University of Califbrnia Riverside Riverside, California 9252 1-0304, USA vahid(ii,cs.ucr.edu","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132862118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

A phase-coherent numerically controlled oscillator based on pipeline architecture 基于流水线结构的相参数控振荡器

Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372) Pub Date : 1998-09-13 DOI: 10.1109/ASIC.1998.723034

P. Nagvajara, T.R. Damarla, J. Wang, S. Chansilp

引用次数: 2