Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)最新文献_第6页

Low-power high-speed 1-V LSI using a 0.25-/spl mu/m MTCMOS/SIMOX technique 采用0.25-/spl mu/m MTCMOS/SIMOX技术的低功耗高速1-V LSI

Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372) Pub Date : 1998-09-13 DOI: 10.1109/ASIC.1998.722812

S. Shigematsu, T. Hatano, Y. Tanabe, S. Mutoh

引用次数: 1

A /spl mu/Watt postage stamp PC A /spl亩/瓦特邮票PC机

Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372) Pub Date : 1998-09-13 DOI: 10.1109/ASIC.1998.722819

David G. England

引用次数: 0

Efficient high-speed CIC decimation filter 高效高速CIC抽取滤波器

Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372) Pub Date : 1998-09-13 DOI: 10.1109/ASIC.1998.722984

Kei-Yong Khoo, Zhan Yu, A. Wilson

引用次数: 23

Architectural level hierarchical power estimation of control units 控制单元的体系结构级分层功率估计

Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372) Pub Date : 1998-09-13 DOI: 10.1109/ASIC.1998.722905

R.Y. Chen, M. J. Irwin, R. Bajwa

{"title":"Architectural level hierarchical power estimation of control units","authors":"R.Y. Chen, M. J. Irwin, R. Bajwa","doi":"10.1109/ASIC.1998.722905","DOIUrl":"https://doi.org/10.1109/ASIC.1998.722905","url":null,"abstract":"This paper presents a novel technique used to estimate the power dissipation of control units at the architectural level. Based on the instruction stream and output signals of the control units, this approach provides accurate power consumption data without any knowledge of their logic structures. It is a top-down hierarchical method which can handle random logic control units as well as ROM and PLA based control units. The upper-level power estimation analyses the instructions through their formats, and produces an efficient energy model for instruction format transitions. The lower-level estimation is performed for each instruction format by tracing the transitions of output signals. For simple logic control units, predictable internal signals can be used instead of output signals. We have applied this technique into an architectural level power estimator of a real processor. The accuracy of the estimator is demonstrated by comparing the power values it produces against measurements made by a gate level power simulator for the same benchmark set. The results show that our estimation approach for control units can provide more accurate solution than statistical analysis and is more efficient than conventional look-up table based methods.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132739068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Digital Sianal Processing And Image Processing 数字信号处理和图像处理

Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372) Pub Date : 1998-09-13 DOI: 10.1109/ASIC.1998.723018

Y. Yung, B. Cook

引用次数: 0

A low power transregional MOSFET model for complete power-delay analysis of CMOS gigascale integration (GSI) 用于CMOS千兆级集成(GSI)完全功率延迟分析的低功率跨区域MOSFET模型

Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372) Pub Date : 1998-09-13 DOI: 10.1109/ASIC.1998.722816

B. Austin, Keith A Bowman, Xinghai Tang, James D. Meindl

{"title":"A low power transregional MOSFET model for complete power-delay analysis of CMOS gigascale integration (GSI)","authors":"B. Austin, Keith A Bowman, Xinghai Tang, James D. Meindl","doi":"10.1109/ASIC.1998.722816","DOIUrl":"https://doi.org/10.1109/ASIC.1998.722816","url":null,"abstract":"A new compact transregional model for conventional surface channel inversion MOSFETs with continuous and smooth transitions at regional boundaries is introduced. The model, verified against MEDICI and HSPICE, describes all regions of operation, namely, subthreshold, linear, and saturation while including the effects of 1) carrier velocity saturation, 2) vertical and lateral high field mobility degradation, and 3) threshold voltage roll-off, all prominent characteristics of sub-micron devices. The key contribution of this model is the physical insight into the on/off current trade-off that ensues with voltage scaling and will be vital to future low power design. Utilizing the model for a complete power-delay analysis of CMOS circuit designs, analytical expressions are derived for: 1) propagation delay, 2) short circuit power (P/sub SC/), and 3) static power (P/sub Static/). Results from the total power (P/sub Total/) consumption analysis indicate that P/sub SC/ and P/sub Static/ may constitute over 1/3 of P/sub Total/ in future low power/high performance CMOS GSI.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115593730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 40

A 10-bit 20-Msample/s ADC for low-power and low-voltage applications 用于低功耗和低电压应用的10位20毫秒采样/秒ADC

Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372) Pub Date : 1998-09-13 DOI: 10.1109/ASIC.1998.722802

G. Sou, G. Lu, G. Klisnick, M. Redon

引用次数: 1

Design of integrated systems including MEMS and ASICs 集成系统的设计，包括MEMS和asic

Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372) Pub Date : 1998-09-13 DOI: 10.1109/ASIC.1998.723044

J. Gilbert, S. Bart, B. Romanowicz

引用次数: 3

A versatile and scalable MIMD architecture for studio quality motion estimation 用于工作室质量运动估计的通用和可扩展的MIMD架构

Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372) Pub Date : 1998-09-13 DOI: 10.1109/ASIC.1998.723021

F. Mombers, S. Dogimont, D. Mlynek, P. Garino

引用次数: 0

A novel scheduling-based CAD methodology for exploring the design space of ASICs for low power 一种新的基于调度的CAD方法，用于探索低功耗专用集成电路的设计空间

Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372) Pub Date : 1998-09-13 DOI: 10.1109/ASIC.1998.722814

A. Kumar, M. Bayoumi

引用次数: 4