{"title":"A /spl亩/瓦特邮票PC机","authors":"David G. England","doi":"10.1109/ASIC.1998.722819","DOIUrl":null,"url":null,"abstract":"This paper gives details of a Intel386/sup TM/ microprocessor based system in a single package. The functionality of this single device is somewhat equivalent to a 1990 PC. However, the design includes many features that significantly reduce power consumption. The design incorporates 'Few Chip Package (FCP)' technology to marry 0.35 micron logic die and 0.35 micron flash memory technologies in a single 23 mm package. The main feature of the part is its reduced average power consumption of less than 1 mW in target applications.","PeriodicalId":104431,"journal":{"name":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1998-09-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A /spl mu/Watt postage stamp PC\",\"authors\":\"David G. England\",\"doi\":\"10.1109/ASIC.1998.722819\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper gives details of a Intel386/sup TM/ microprocessor based system in a single package. The functionality of this single device is somewhat equivalent to a 1990 PC. However, the design includes many features that significantly reduce power consumption. The design incorporates 'Few Chip Package (FCP)' technology to marry 0.35 micron logic die and 0.35 micron flash memory technologies in a single 23 mm package. The main feature of the part is its reduced average power consumption of less than 1 mW in target applications.\",\"PeriodicalId\":104431,\"journal\":{\"name\":\"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1998-09-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASIC.1998.722819\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings Eleventh Annual IEEE International ASIC Conference (Cat. No.98TH8372)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASIC.1998.722819","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This paper gives details of a Intel386/sup TM/ microprocessor based system in a single package. The functionality of this single device is somewhat equivalent to a 1990 PC. However, the design includes many features that significantly reduce power consumption. The design incorporates 'Few Chip Package (FCP)' technology to marry 0.35 micron logic die and 0.35 micron flash memory technologies in a single 23 mm package. The main feature of the part is its reduced average power consumption of less than 1 mW in target applications.