Modular realization of threshold logic gates for high performance digital signal processing applications

Abstract

In this paper, a modular realization of capacitive threshold logic (CTL) gates is proposed, offering significant advantages in terms of silicon area and speed in certain applications. The generic CTL circuit architecture is presented, its main building blocks are introduced and the operation of the circuit is discussed. A layout design automation environment is presented for the automatic generation of mask-level layout of CTL gates, using conventional CMOS fabrication technology.