A nonlinear integrator model used to design a robust 16-bit, 40 kSPS switched capacitor sigma-delta modulator

Abstract

The design of robust high-order sigma-delta modulator circuits is difficult since linear analysis cannot be used to accurately estimate performance characteristics such as signal-to-noise ratio (SNR) and signal-to-distortion ratio (SDR). Designers rely on time-domain simulation of the modulator loop to evaluate these critical performance characteristics. A new model for a switched capacitor integrator is presented and evaluated. Accurate models of the integrators are developed from integrator circuit simulation. The model provides the speed of look-up table based modulator simulation while also providing useful input for design modification not available when using look-up table based simulation methods.