Power electronic devices and components最新文献

{"title":"Maximum Peak Current and Junction-to-ambient Delta-temperature Investigation in GaN FETs Parallel Connection","authors":"Vincenzo Barba ,&nbsp;Salvatore Musumeci ,&nbsp;Marco Palma ,&nbsp;Radu Bojoi","doi":"10.1016/j.pedc.2023.100035","DOIUrl":"10.1016/j.pedc.2023.100035","url":null,"abstract":"<div><p>In power inverter applications, Gallium Nitride (GaN) technology demonstrates advantages of energy conversion quality, power density, and efficiency, such as in medium to high switching frequency motor drive. The parallel connection of GaN FETs increases the current capability of power switches. In the parallel connection, wide threshold voltage <span><math><msub><mi>V</mi><mi>GSth</mi></msub></math></span> spread of GaN FETs is the main parameter to consider. This paper investigates peak current and thermal response depending on the number <span><math><mi>N</mi></math></span> of GaN FETs connected in parallel and the operating conditions. This study provides new insights for the design of a board with a large number of paralleled GaN FETs. The target is to show how the peak current and the maximum junction-to-ambient delta-temperature are related to the <span><math><msub><mi>V</mi><mi>GSth</mi></msub></math></span> spread. In order to separate the PCB or parasitic impedance effects from the device parameter spread one into the analysis, it was agreed to proceed by running simulations with a validated GaN FET model. A comparison between the maximum spread declared in the datasheet, to the typical one that can be found on the same production lot is carried out. Furthermore, switching operation and temperature evaluations are analyzed.</p></div>","PeriodicalId":74483,"journal":{"name":"Power electronic devices and components","volume":"5 ","pages":"Article 100035"},"PeriodicalIF":0.0,"publicationDate":"2023-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"41407541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Characterization of the novel ICeGaN 650V/ 8.5 A, 200 mΩ power device technology","authors":"K. Mukherjee,&nbsp;M. Arnold,&nbsp;J. Zhang,&nbsp;K. Ledins,&nbsp;M. Michalak,&nbsp;O. Fung,&nbsp;L. Efthymiou,&nbsp;Z. Ansari,&nbsp;G. Longobardi,&nbsp;F. Udrea","doi":"10.1016/j.pedc.2023.100037","DOIUrl":"10.1016/j.pedc.2023.100037","url":null,"abstract":"<div><p>This work reports on the static and dynamic performance of the state-of-the-art 650 V ICeGaN™ (Integrated Circuit Enhancement GaN) power switch with an ON-state resistance <em>R_on</em> of 200 mΩ. Through the monolithic integration of a novel gate interface with a p-GaN HEMT, these switches operate on a wide operational gate voltage window up to 20 V, making them exceptional in their compatibility with standard Si gate drivers or controller chips. Along with enhanced gate reliability, the devices demonstrate excellent static and switching performance with a high breakdown voltage and very low output charge (<em>Q_oss</em>) and gate charge (<em>Q_g</em>) metrics. They display minimal parameter drifts after 48 h of High Temperature Reverse Bias (HTRB) stress, validating the off-state reliability performance.</p></div>","PeriodicalId":74483,"journal":{"name":"Power electronic devices and components","volume":"5 ","pages":"Article 100037"},"PeriodicalIF":0.0,"publicationDate":"2023-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"44206323","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Lifetime model adjustments for GaN cascodes as a base for inverter lifetime estimation","authors":"Florian Lippold,&nbsp;Regine Mallwitz","doi":"10.1016/j.pedc.2023.100039","DOIUrl":"10.1016/j.pedc.2023.100039","url":null,"abstract":"<div><p>Lifetime models for GaN power semiconductors are essential for a reliable and long-term stable design of complete power electronics systems. Load power cycling investigates the connections between the semiconductor chip, the package and the system. In this paper, various GaN cascodes in TO-247 packages were cycled. The results were analyzed, so that empiric lifetime models could be derived. The aging of bond wires is mainly the cause for the end of life and therefore the Coffin-Manson-Approach can be used for the GaN lifetime modelling. The lifetime of an inverter equipped with this GaN devices is estimated and is assessed as being high.</p></div>","PeriodicalId":74483,"journal":{"name":"Power electronic devices and components","volume":"5 ","pages":"Article 100039"},"PeriodicalIF":0.0,"publicationDate":"2023-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"46115078","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Growth of p-type GaN – The role of oxygen in activation of Mg-doping","authors":"Ashutosh Kumar ,&nbsp;Martin Berg ,&nbsp;Qin Wang ,&nbsp;Michael Salter ,&nbsp;Peter Ramvall","doi":"10.1016/j.pedc.2023.100036","DOIUrl":"10.1016/j.pedc.2023.100036","url":null,"abstract":"<div><p>The effects of N₂ and O₂:N₂ (1:1) as ambient gases during activation annealing of Mg as p-type doping of GaN have been investigated. The purpose was to understand the mechanisms involved and especially the impact of O₂ on the resulting hole concentration and hole mobility. The addition of O₂ to the ambient gas during annealing is known to be very effective in reducing the H level of the Mg-doped GaN layer, but the maximum achievable hole concentration and mobility, as determined by Hall characterization, is still higher with pure N₂. The difference is explained by an in-diffusion of O to the GaN layer acting as n-dopant and thus giving rise to a compensation effect.</p><p>It is found that to a large degree only the Mg-H complexes at substitutional (Mg_Ga), i.e., the electrically active acceptor sites that provide free holes, are activated by annealing with N₂ only as ambient gas, while annealing with O₂:N₂ (1:1) also dissociates electrically inactive Mg-H complexes resulting in much less residual H. Thus, the residual H level in relation to the Mg level after activation annealing with N₂ only may provide a representative measure of the resulting free hole concentration of the Mg-doped GaN layer.</p></div>","PeriodicalId":74483,"journal":{"name":"Power electronic devices and components","volume":"5 ","pages":"Article 100036"},"PeriodicalIF":0.0,"publicationDate":"2023-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"44344758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Impact of post-deposition anneal on ALD Al2O3/etched GaN interface for gate-first MOSc-HEMT","authors":"P. Fernandes Paes Pinto Rocha ,&nbsp;L. Vauche ,&nbsp;B. Mohamad ,&nbsp;W. Vandendaele ,&nbsp;E. Martinez ,&nbsp;M. Veillerot ,&nbsp;T. Spelta ,&nbsp;N. Rochat ,&nbsp;R. Gwoziecki ,&nbsp;B. Salem ,&nbsp;V. Sousa","doi":"10.1016/j.pedc.2023.100033","DOIUrl":"10.1016/j.pedc.2023.100033","url":null,"abstract":"<div><p>MOS High Electron Mobility Transistors (MOS-HEMTs) may suffer from V_TH instability and hysteresis reducing device performances. Post-Deposition Anneal (PDA) of the Atomic-Layer Deposited (ALD) dielectric has the potential to increase MOS-HEMT performances but needs to be compatible with the actual integration (at CEA Leti: fully recessed Gate First MOS-channel HEMT process flow). In this work, the impact of different PDA temperatures on flat-band voltage (V_FB) and its hysteresis (ΔV_FB) for Al₂O₃ deposited on etched GaN substrates is investigated using MOS capacitors (MOSCAPs). Material properties are analyzed by Hard X-Ray Photoelectron Spectroscopy (HAXPES), Fourier Transform Infrared Spectroscopy (FTIR) and Time-of-Flight Secondary Ion Mass Spectrometry (ToF-SIMS) analyses. With increasing PDA temperature up to 500°C: (i) ΔV_FB decreases and is explained by the reduction of Ga-O bonds at Al₂O₃/GaN interface and O-H groups in Al₂O₃ (ii) V_FB decreases and could be explained by the reduction of fluorine impurity concentration in Al₂O₃. For 600°C PDA, Grazing Incidence X-Ray Diffraction (GIXRD) analysis shows a small crystallized κ-Al₂O₃ signal on etched GaN contrary to the as-grown GaN. The onset of this crystallization could explain the degradation in breakdown field for PDA above 500°C observed on MOSCAPs after the Gate-First process flow overall thermal budget. Therefore, the optimized PDA temperature suggested for a fully recessed Gate First MOS-channel HEMT is 500°C.</p></div>","PeriodicalId":74483,"journal":{"name":"Power electronic devices and components","volume":"4 ","pages":"Article 100033"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43720657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Advantages of the extended finite element method for the analysis of crack propagation in power modules","authors":"Kenneth Chimezie Nwanoro,&nbsp;Hua Lu,&nbsp;Chunyan Yin,&nbsp;Chris Bailey","doi":"10.1016/j.pedc.2022.100027","DOIUrl":"https://doi.org/10.1016/j.pedc.2022.100027","url":null,"abstract":"<div><p>The techniques of extended finite element method, level set method and the submodelling approach are implemented in this study to model crack and crack growth in ultrasonically bonded thick aluminium wire for the IGBT power electronics modules under different loading conditions for the purpose of lifetime prediction and reliability assessment during design and manufacturing stages. The crack growth and lifetime prediction were performed under cyclic fatigue passive thermal cycling and active power cycling for the bond wire lift-off failure mechanism while the J-integral for different heel crack lengths are predicted under mechanical loads. The analyses showed that the techniques implemented in this paper are effective for modelling such complex geometries and loading conditions and can easily be integrated in a virtual design platform for power electronics. The accuracy of the technique is evaluated by comparing with trends in the published experimental tests and simulation results as well as the standard finite element method which are all in a good agreement. The wire bond crack growth rate under cyclic loading is strongly influenced by the bond thickness and loading conditions.</p></div>","PeriodicalId":74483,"journal":{"name":"Power electronic devices and components","volume":"4 ","pages":"Article 100027"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"49817870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"PECVD SiNx passivation with more than 8 MV/cm breakdown strength for GaN-on-Si wafer stress management","authors":"Matthias Moser ,&nbsp;Mamta Pradhan ,&nbsp;Mohammed Alomari ,&nbsp;Michael Heuken ,&nbsp;Thomas Schmitt ,&nbsp;Ingmar Kallfass ,&nbsp;Joachim N. Burghartz","doi":"10.1016/j.pedc.2022.100032","DOIUrl":"10.1016/j.pedc.2022.100032","url":null,"abstract":"<div><p>In this work, multi-layer PECVD <span><math><msub><mtext>SiN</mtext><mi>x</mi></msub></math></span>/<span><math><msub><mtext>SiN</mtext><mi>x</mi></msub></math></span> and <span><math><msub><mtext>SiN</mtext><mi>x</mi></msub></math></span>/<span><math><msub><mrow><mi>SiO</mi></mrow><mi>y</mi></msub></math></span> passivations are developed featuring very high soft breakdown strength and tunable stress properties, which would allow for stress engineering and wafer bow minimization. AlGaN/GaN-on-Si wafers (150 mm) with very low initial bow (<span><math><mrow><mo>&lt;</mo><mn>5</mn></mrow></math></span> <span><math><mrow><mi>μ</mi></mrow></math></span>m) are processed in a CMOS compatible manner. The effect of the major processing steps, namely passivation and metal deposition, on the wafer bow is continuously monitored. In this process aimed at power devices, relatively thick passivation is needed (1.5 <span><math><mrow><mi>μ</mi></mrow></math></span>m), which would induce very high stresses on the wafer if a single-layer deposition is applied. Hence, deposition of multiple layers is explored through mechanical modelling and simulation, leading to a stress-free passivation. The optimized multi-layer dielectric consists of two different <span><math><msub><mtext>SiN</mtext><mi>x</mi></msub></math></span> single layers (referred to as T40 and R100), which have opposite stress properties, with T40 being tensile and R100 being compressive. By adjusting the thickness ratio of both layers and the number of total layers, mechanical stress within the multi-layer can be neutralized to achieve stress-free deposition. In addition, the optimization of the film properties includes the electrical properties of the passivation, and is designed primarily for high voltage applications. The developed <span><math><msub><mtext>SiN</mtext><mi>x</mi></msub></math></span>/<span><math><msub><mtext>SiN</mtext><mi>x</mi></msub></math></span> passivation has a soft breakdown strength with more than 8 MV/cm, and leakage currents below 1 nA/mm² up to soft breakdown. After dielectric development, Schottky and MIS device characteristics with <span><math><msub><mtext>SiN</mtext><mi>x</mi></msub></math></span>/<span><math><msub><mtext>SiN</mtext><mi>x</mi></msub></math></span> multi-layers are characterized in DC and pulse mode measurements. As measurements suggest, the developed passivation is suitable for GaN-on-Si HEMT applications.</p></div>","PeriodicalId":74483,"journal":{"name":"Power electronic devices and components","volume":"4 ","pages":"Article 100032"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43293419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Investigation on safe-operating-area degradation and failure modes of SiC MOSFETs under repetitive short-circuit conditions","authors":"Ziyang Zhang,&nbsp;Lin Liang,&nbsp;Haoyang Fei","doi":"10.1016/j.pedc.2022.100026","DOIUrl":"10.1016/j.pedc.2022.100026","url":null,"abstract":"<div><p>The safe operating area is an operating area with high reliability for SiC MOSFET, and its degradation may cause power electronic system failure. The safe-operating-area degradation and the failure modes of 1200 V/66A SiC MOSFET caused by repetitive short-circuit stress with different short-circuit durations and repetition rates are investigated. A short circuit test platform with circuit protection is configured to degrade DUT(device under test), and the safe operating area is characterized after repetitive short circuit stress is applied. The degradation mechanism of the safe operating area is explained by the 1-D electro-thermal coupling model based on Sentaurus TCAD. When the critical short-circuit duration is 12μs, the single short-circuit failure mode of DUT with 400 V dc-bus voltage is a gate-source short-circuit failure. From the short circuit test result, the failure modes under repetitive short-circuit conditions include gate-source short-circuit failure and thermal runaway, depending on the repetitive rates. For the same short-circuit time interval, when the short-circuit duration is 10μs, the weakest boundary of the safe operating area is the blocking voltage. When the short-circuit duration is 2μs, all three boundaries of the safe operating area are contracted. These results are confined to 400 V dc-bus voltage, 25 °C case temperature, and 18 V/-3 V gate-source voltage.</p></div>","PeriodicalId":74483,"journal":{"name":"Power electronic devices and components","volume":"4 ","pages":"Article 100026"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"44044941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"ICeGaNTM technology: The easy-to-use and self-protected GaN power IC","authors":"Giorgia Longobardi,&nbsp;Loizos Efthymiou,&nbsp;John Findlay,&nbsp;Andrea Bricconi,&nbsp;Peter Comiskey,&nbsp;Martin Arnold,&nbsp;David Miller,&nbsp;Florin Udrea","doi":"10.1016/j.pedc.2022.100028","DOIUrl":"10.1016/j.pedc.2022.100028","url":null,"abstract":"<div><p>This work provides an overview of the current state of technology in the field of lateral GaN power devices and presents the characteristics of the main commercially available 650 V GaN power devices and ICs. A comparison is given, both in terms of key parameters as well as of the availability of complex functionality through integration of additional smart features. The features of our new technology, termed ICeGaN™, are presented in this context, focusing on the benefits that may be derived when ICeGaN™ devices are used in common applications. ICeGaN™ is a new concept of a smart HEMT which offers ease-of-use, sensing and protection functions without sacrificing performance.</p></div>","PeriodicalId":74483,"journal":{"name":"Power electronic devices and components","volume":"4 ","pages":"Article 100028"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43363874","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A review of PETT oscillation's characteristics, mechanism, and suppression methods in the IGBT device","authors":"Ganyu Feng ,&nbsp;Xuebao Li ,&nbsp;Xinling Tang ,&nbsp;Xiaoguang Wei ,&nbsp;Zhibin Zhao","doi":"10.1016/j.pedc.2022.100030","DOIUrl":"10.1016/j.pedc.2022.100030","url":null,"abstract":"<div><p>In practical application, there are many parallel insulated gate bipolar transistor (IGBT) chips and anti-parallel fast recovery diode (FRD) chips in the IGBT devices. Because of the interactions between parasitic inductance and chip capacitance, plasma extraction transit time (PETT) oscillation might raise during the operation of IGBT device. The PETT oscillation, whose frequency ranges from 1 MHz to 700 MHz, may induce interference on driver circuits, and then cause the device failure. Moreover, the electromagnetic disturbance will affect the secondary devices. Therefore, it should be seriously considered in the design of the packaging to suppress PETT oscillation. The mechanism of PETT oscillation is complex, and its electrical characteristics are sensitive to the chip's parameters, load current, and DC link voltage. Hence, PETT oscillation is an important problem to be solved in device packaging design. In this paper, the characteristics, mechanism, and suppression methods of PETT oscillation are summarized. Based on the systematic summary, various suppression methods are compared and analyzed. Furthermore, the future research issues are prospected.</p></div>","PeriodicalId":74483,"journal":{"name":"Power electronic devices and components","volume":"4 ","pages":"Article 100030"},"PeriodicalIF":0.0,"publicationDate":"2023-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"48075215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}