Impact of post-deposition anneal on ALD Al2O3/etched GaN interface for gate-first MOSc-HEMT

Abstract

MOS High Electron Mobility Transistors (MOS-HEMTs) may suffer from V_TH instability and hysteresis reducing device performances. Post-Deposition Anneal (PDA) of the Atomic-Layer Deposited (ALD) dielectric has the potential to increase MOS-HEMT performances but needs to be compatible with the actual integration (at CEA Leti: fully recessed Gate First MOS-channel HEMT process flow). In this work, the impact of different PDA temperatures on flat-band voltage (V_FB) and its hysteresis (ΔV_FB) for Al₂O₃ deposited on etched GaN substrates is investigated using MOS capacitors (MOSCAPs). Material properties are analyzed by Hard X-Ray Photoelectron Spectroscopy (HAXPES), Fourier Transform Infrared Spectroscopy (FTIR) and Time-of-Flight Secondary Ion Mass Spectrometry (ToF-SIMS) analyses. With increasing PDA temperature up to 500°C: (i) ΔV_FB decreases and is explained by the reduction of Ga-O bonds at Al₂O₃/GaN interface and O-H groups in Al₂O₃ (ii) V_FB decreases and could be explained by the reduction of fluorine impurity concentration in Al₂O₃. For 600°C PDA, Grazing Incidence X-Ray Diffraction (GIXRD) analysis shows a small crystallized κ-Al₂O₃ signal on etched GaN contrary to the as-grown GaN. The onset of this crystallization could explain the degradation in breakdown field for PDA above 500°C observed on MOSCAPs after the Gate-First process flow overall thermal budget. Therefore, the optimized PDA temperature suggested for a fully recessed Gate First MOS-channel HEMT is 500°C.