Power electronic devices and components最新文献

Simulation and experimental analysis of layout-dependent thermal performance of PCB-embedded resistive heating elements pcb内嵌式电阻式加热元件布局热性能的仿真与实验分析

Power electronic devices and components Pub Date : 2026-03-01 Epub Date: 2026-01-24 DOI: 10.1016/j.pedc.2026.100136

Vlad Cristescu, Alexandra Fodor, Liviu Viman

{"title":"Simulation and experimental analysis of layout-dependent thermal performance of PCB-embedded resistive heating elements","authors":"Vlad Cristescu, Alexandra Fodor, Liviu Viman","doi":"10.1016/j.pedc.2026.100136","DOIUrl":"10.1016/j.pedc.2026.100136","url":null,"abstract":"<div><div>This study examines advanced thermal management strategies for printed circuit boards (PCBs) with embedded heating elements, focusing on minimizing heat propagation toward temperature-sensitive components. The research investigates how design and material modifications influence thermal containment and temperature uniformity across the board. Several PCB configurations were analyzed, including the removal of copper pours on internal layers beneath the heating element, variation of the clearance between the heating area and adjacent circuitry, the addition of thermal vias versus non-plated through holes (NPTH) or modified copper thicknesses on the top layer. Thermal simulations reveal that a continuous row of thermal vias facilitates lateral heat transfer, reducing isolation efficiency, while NPTH structures limit spreading more effectively. Increasing copper thickness improves temperature uniformity but lowers peak temperature due to reduced electrical resistance which in turn increases power consumption. Conversely, thinner copper layers enable higher surface temperatures at lower current levels but elevate the risk of copper delamination. The findings provide practical design guidelines for minimizing unwanted thermal transfer and improving the reliability of PCBs used in high-temperature applications such as automated soldering, laboratory heating platforms, and precision thermal control systems.</div></div>","PeriodicalId":74483,"journal":{"name":"Power electronic devices and components","volume":"13 ","pages":"Article 100136"},"PeriodicalIF":0.0,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146173506","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Transient current sharing in parallel GaN FETs: The role of parasitic capacitances 并联GaN场效应管的暂态电流分担：寄生电容的作用

Power electronic devices and components Pub Date : 2026-03-01 Epub Date: 2026-02-24 DOI: 10.1016/j.pedc.2026.100138

Salvatore Musumeci PhD , Vincenzo Barba PhD , Michele Pastorelli Professor , Marco Palma MSc

{"title":"Transient current sharing in parallel GaN FETs: The role of parasitic capacitances","authors":"Salvatore Musumeci PhD , Vincenzo Barba PhD , Michele Pastorelli Professor , Marco Palma MSc","doi":"10.1016/j.pedc.2026.100138","DOIUrl":"10.1016/j.pedc.2026.100138","url":null,"abstract":"<div><div>This paper examines the impact of parasitic capacitances on the dynamic current sharing behaviour of Gallium Nitride (GaN) field-effect transistors (FETs) operating in parallel configurations. As GaN technology continues to gain prominence in high-performance power electronic systems, paralleling multiple devices has become a common strategy to increase current-handling capability. However, non-idealities such as parasitic elements introduce significant challenges in achieving balanced current distribution during switching transients. To examine these effects, a custom-designed experimental platform was developed, enabling independent gate control and current measurement for each GaN FET via dedicated source shunt resistors. The test setup facilitates the precise characterisation of transient behavior and allows for detailed analysis under controlled conditions. Complementary simulation studies were conducted to support the experimental results and to identify key parameters influencing transient current mismatch. The paper highlights the critical role of parasitic capacitances—both device-internal and layout-induced—in shaping the peak transient current distribution among parallel devices during turn-on events. A methodology is proposed to estimate the maximum allowable parasitic capacitance that ensures the peak pulse current remains within the safe operating limits specified by device manufacturers. This insight is essential for the robust design of multi-device GaN switching assemblies, where overcurrent during transients can compromise long-term reliability or lead to failure. The outcomes of this research provide practical design guidelines for optimising parallel GaN switch configurations, with particular attention to parasitic management, driver strategy, and layout considerations. These contributions support the development of reliable and high-efficiency GaN-based power modules for advanced power conversion applications.</div></div>","PeriodicalId":74483,"journal":{"name":"Power electronic devices and components","volume":"13 ","pages":"Article 100138"},"PeriodicalIF":0.0,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"147396896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Review of gate driver integrated gate-oxide health monitoring for SiC MOSFETs: Methods, challenges, and perspectives SiC mosfet栅极驱动器集成栅极氧化物健康监测综述：方法、挑战和展望

Power electronic devices and components Pub Date : 2026-03-01 Epub Date: 2026-01-24 DOI: 10.1016/j.pedc.2026.100137

Kun Tan , Haiyang Xie , Bing Ji , Wenping Cao , Cungang Hu , Shu Yang , Xi Tang

{"title":"Review of gate driver integrated gate-oxide health monitoring for SiC MOSFETs: Methods, challenges, and perspectives","authors":"Kun Tan , Haiyang Xie , Bing Ji , Wenping Cao , Cungang Hu , Shu Yang , Xi Tang","doi":"10.1016/j.pedc.2026.100137","DOIUrl":"10.1016/j.pedc.2026.100137","url":null,"abstract":"<div><div>The reliability issue of gate oxide of silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) is still a bottleneck for its wide spread in high-efficiency, high-temperature, and high-frequency power electronics applications, especially where system reliability is critical. The gate oxide degradation can lead to parameter drift, increased losses, and even sudden device failures, posing a serious threat to the robustness of power converters. Realizing online monitoring for the gate oxide is a possibility to diagnose the health status and forecast the remaining lifespan, therefore preventing device and converter from unexpected failure, which further enhance the system reliability. Embedding measurement circuits within the gate driver, leveraging its proximity to the device and ease of integration, has potentials in achieving a non-invasive, fast, and low-cost solution for condition monitoring. This paper provides an overview of the gate oxide degradation mechanism, reviews state-of-the-art online monitoring methods for gate oxide degradation of SiC MOSFETs, and identifies the challenges and limitations in current approaches, highlighting areas where future research is needed to fully realize the robust and intelligent reliability monitoring.</div></div>","PeriodicalId":74483,"journal":{"name":"Power electronic devices and components","volume":"13 ","pages":"Article 100137"},"PeriodicalIF":0.0,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146173573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Stacked high voltage aluminum polymer capacitor without separator, realization and evaluation at 450V 无隔板叠置高压铝聚合物电容器，450V电压下的实现与评价

Power electronic devices and components Pub Date : 2026-03-01 Epub Date: 2026-02-23 DOI: 10.1016/j.pedc.2026.100139

Jonas Wittmaack, Thomas Ebel

引用次数: 0

SOA measurement of SiC MOSFETs using different voltage clamping techniques in DC SSCB 在直流SSCB中使用不同箝位技术的SiC mosfet的SOA测量

Power electronic devices and components Pub Date : 2026-03-01 Epub Date: 2025-12-03 DOI: 10.1016/j.pedc.2025.100134

Imran Zulfiqar, Lin Liang, Zhongqi Guo, Fengming Yang, Xiangyu Wan

{"title":"SOA measurement of SiC MOSFETs using different voltage clamping techniques in DC SSCB","authors":"Imran Zulfiqar, Lin Liang, Zhongqi Guo, Fengming Yang, Xiangyu Wan","doi":"10.1016/j.pedc.2025.100134","DOIUrl":"10.1016/j.pedc.2025.100134","url":null,"abstract":"<div><div>DC systems have received a lot of attention in recent years for their superior performance and reliability compared to AC systems, especially in applications such as DC microgrids, electric aircraft, battery protection, photovoltaics, and marine power distribution. DC semiconductor circuit breakers (DCCBs) using SiC MOSFETs are an ideal solution for these systems because they offer high input speeds. However, little is known about the performance and reliability of SiC MOSFET under DCCB conditions, especially the different voltage stabilization techniques. There are three main contributions of this article. First, evaluate the safe operating area (SOA) and characteristics of SiC MOSFET for DCCB applications, focusing on three voltage clamping methods: RCD, MOV, and a combination of both. Second, it provides a comprehensive quantifying investigation of the drain–source current <span><math><msub><mrow><mi>I</mi></mrow><mrow><mi>d</mi></mrow></msub></math></span>. The RCD method can interrupt currents up to 5.25 times the rated current in single-pulse tests, while the MOV method supports up to 4.83 times, and the combined method up to 4.6 times. Third, in repetitive tests, the RCD, MOV, and combined methods sustained 1122, 2078, and 2842 interruptions, respectively, at 2.25 times the rated current. The total energy over the lifespan is 11.62MJ for the RCD, 21.52MJ for the MOV, and 29.44MJ for the hybrid RCD-MOV. Thermal failure was the primary cause of degradation. The findings emphasize the need for optimized voltage clamping strategies to improve the performance, reliability, and SOA of SiC MOSFETs in DCCB applications.</div></div>","PeriodicalId":74483,"journal":{"name":"Power electronic devices and components","volume":"13 ","pages":"Article 100134"},"PeriodicalIF":0.0,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145760799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Impact of switching interaction on FWD chip size selection for an asynchronous boost converter 开关相互作用对异步升压变换器FWD芯片尺寸选择的影响

Power electronic devices and components Pub Date : 2026-03-01 Epub Date: 2025-12-15 DOI: 10.1016/j.pedc.2025.100135

Hyunyong Park, Yeonjun Kim, Hyemin Kang

{"title":"Impact of switching interaction on FWD chip size selection for an asynchronous boost converter","authors":"Hyunyong Park, Yeonjun Kim, Hyemin Kang","doi":"10.1016/j.pedc.2025.100135","DOIUrl":"10.1016/j.pedc.2025.100135","url":null,"abstract":"<div><div>This paper investigates how switching interaction between power semiconductor devices affects the selection of free-wheeling diode chip size in asynchronous boost converters. Coupled switching losses were measured through double pulse tests, and conduction losses were characterized independently. The results reveal that increasing the FWD chip size reduces its conduction loss, but can significantly increase the overall switching losses due to interaction with the power switch, especially when the switch is small. Furthermore, FWD chip size selection for the efficiency depends strongly on system operating conditions such as switching frequency, duty ratio, input voltage, and temperature. The analysis shows that a simplified loss calculation ignoring device interaction can result in significant errors in FWD selection, particularly at high switching frequencies, voltages, or temperatures, which are increasingly relevant with the adoption of SiC technology. These results demonstrate that switching losses must be measured with the actual device pair to ensure energy-efficient converter design.</div></div>","PeriodicalId":74483,"journal":{"name":"Power electronic devices and components","volume":"13 ","pages":"Article 100135"},"PeriodicalIF":0.0,"publicationDate":"2026-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145792132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Systematic investigation on the effects of tracks’ mutual coupling on a GaN-based three-level bridge leg 轨道互耦对氮化镓三水平桥腿影响的系统研究

Power electronic devices and components Pub Date : 2025-12-01 Epub Date: 2025-09-18 DOI: 10.1016/j.pedc.2025.100120

Maria Giorgia Spitaleri , Francesco Iannuzzo , Emre Gurpinar , Giacomo Scelba

引用次数: 0

Three-Phase Active Split-Source Inverter with step-up/step-down DC bus voltage capabilities for traction application 三相有源分源逆变器，具有升压/降压直流母线电压能力，用于牵引应用

Power electronic devices and components Pub Date : 2025-12-01 Epub Date: 2025-11-19 DOI: 10.1016/j.pedc.2025.100133

Antoine Sabrié , Alexandre Battiston , Jean-Yves Gauthier , Xuefang Lin-shi

引用次数: 0

Modelling of SiC and GaN transistors based on pulsed S-parameter measurements 基于脉冲s参数测量的SiC和GaN晶体管建模

Power electronic devices and components Pub Date : 2025-12-01 Epub Date: 2025-08-05 DOI: 10.1016/j.pedc.2025.100108

Martin Hergt , Bernhard Hammer , Martin Sack , Lukas W. Mayer , Sebastian Nielebock , Marc Hiller

引用次数: 0

Chip size dependent dynamic behavior of SiC MOSFETs with edge termination 芯片尺寸对边缘端接SiC mosfet动态特性的影响

Power electronic devices and components Pub Date : 2025-12-01 Epub Date: 2025-08-28 DOI: 10.1016/j.pedc.2025.100110

Y. Kim, H. Kang

{"title":"Chip size dependent dynamic behavior of SiC MOSFETs with edge termination","authors":"Y. Kim, H. Kang","doi":"10.1016/j.pedc.2025.100110","DOIUrl":"10.1016/j.pedc.2025.100110","url":null,"abstract":"<div><div>This study investigates the impact of the active-to-termination area ratio on the dynamic behavior of SiC MOSFETs. As the chip size decreases, the turn-on speed increases due to the reduced input capacitance. However, during the turn-off transient, a <em>dV/dt</em> reversal effect is observed, in which the switching speed decreases despite the overall reduction in parasitic capacitance. This effect arises because, in smaller devices, the edge termination region becomes relatively larger compared to the active region, causing a greater portion of the drain current to flow into the termination region. As a result, the charging of the drain-to-source capacitance in the active region, which dominates the switching transition, slows down. Experimental and mixed-mode simulations confirm that this effect is more pronounced at lower current densities. The study further examines the effect of gate driver capability, showing that a gate driver with high sinking/sourcing capability only maximizes switching frequency. Additionally, thermal resistance and drain-to-source capacitance charging delay limit the maximum switching frequency in smaller devices. These results demonstrate that the active-to-termination area ratio significantly influences the switching characteristics of SiC MOSFETs, particularly in turn-off behavior and frequency limitations.</div></div>","PeriodicalId":74483,"journal":{"name":"Power electronic devices and components","volume":"12 ","pages":"Article 100110"},"PeriodicalIF":0.0,"publicationDate":"2025-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145048811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0