Power electronic devices and components最新文献

Parametric Life Cycle Assessment (LCA) of power modules 电源模块参数生命周期评估（LCA）

Power electronic devices and components Pub Date : 2025-06-26 DOI: 10.1016/j.pedc.2025.100105

Li Fang , Lucas Riondet , Fatimata-Fatim Diarrassouba , Maud Rio , Pierre Lefranc , Jean-Christophe Crébier

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Multi-parameter detection of bond wire lift-off, current, and temperature in IGBT modules via gate voltage waveforms and CNNs with digital gate control 通过栅极电压波形和带有数字栅极控制的cnn实现IGBT模块中键合线升力、电流和温度的多参数检测

Power electronic devices and components Pub Date : 2025-06-24 DOI: 10.1016/j.pedc.2025.100106

Thatree Mamee , Katsuhiro Hata , Makoto Takamiya , Takayasu Sakurai , Shin-ichi Nishizawa , Wataru Saito

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400V SiC MOSFET empowering three-level topologies for highly efficient applications from motor-drives to AI 400V SiC MOSFET支持三级拓扑结构，可用于从电机驱动器到AI的高效应用

Power electronic devices and components Pub Date : 2025-06-16 DOI: 10.1016/j.pedc.2025.100104

Ralf Siemieniec, Martin Wattenberg, Ertugrul Kocaaga, Sriram Jagannath, Elvir Kahrimanovic, Jyotshna Bhandari, Heejae Shim, Alberto Pignatelli

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Investigation on the high temperature behaviour of p-GaN HEMTs by different temperature sensitive electrical parameters 不同温敏电学参数对p-GaN hemt高温行为的研究

Power electronic devices and components Pub Date : 2025-06-05 DOI: 10.1016/j.pedc.2025.100103

Lukas Hein, Maximilian Goller, Gengqi Li, Marius Lößner, Josef Lutz, Thomas Basler

{"title":"Investigation on the high temperature behaviour of p-GaN HEMTs by different temperature sensitive electrical parameters","authors":"Lukas Hein, Maximilian Goller, Gengqi Li, Marius Lößner, Josef Lutz, Thomas Basler","doi":"10.1016/j.pedc.2025.100103","DOIUrl":"10.1016/j.pedc.2025.100103","url":null,"abstract":"<div><div>Due to recent improvements and technical advantages in applications with high switching frequencies, research is increasingly focusing on GaN high electron mobility transistors (HEMTs). An accurate temperature determination is thereby of particular importance to give precise lifetime estimations and define safe operation areas. This work investigates on the temperature estimation by means of the temperature sensitive electrical parameters (TSEPs) <em>R</em><sub>DS,on</sub> (<em>T</em>) and <em>V</em><sub>GS</sub> (<em>T</em>) of GIT-type transistors, supported by an IR-camera. Several <em>Z</em><sub>th</sub> characteristics were measured, whereby the temperature estimation with <em>V</em><sub>GS</sub> (<em>T</em>) appears to be superior. Furthermore, the investigation includes static and dynamic characterization as well as power cycling tests (PCT) with switching losses at high temperature above the datasheet limit of 150°C. The device operates stable and reliable at a junction temperature of 175°C in the PCT.</div></div>","PeriodicalId":74483,"journal":{"name":"Power electronic devices and components","volume":"12 ","pages":"Article 100103"},"PeriodicalIF":0.0,"publicationDate":"2025-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144632381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Volume reduction of magnetic components in DC/DC converters for fuel cell vehicles 燃料电池汽车DC/DC变换器中磁性元件体积减小

Power electronic devices and components Pub Date : 2025-06-02 DOI: 10.1016/j.pedc.2025.100101

Jonas Pfeiffer, Manfred Wohlstreicher, Philemon Wrensch, Michael Schmidhuber

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Declaration/Conflict of Interest statement were not included in the published version of the following article, that appeared in issue Volume 5 2023 of Power Electronic Devices and Components 声明/利益冲突声明不包括在以下文章的发布版本中，该文章出现在2023年第5期《电力电子器件和组件》中

Power electronic devices and components Pub Date : 2025-06-01 DOI: 10.1016/j.pedc.2025.100094

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Evaluating current sensing methods for accurate characterization in small chip size SiC MOSFETs 评估在小片尺寸SiC mosfet中精确表征的电流传感方法

Power electronic devices and components Pub Date : 2025-06-01 DOI: 10.1016/j.pedc.2025.100102

Y. Kim, H. Park, S. Yoon, H. Kang

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Physical and electrical characterizations of low n-doped MOCVD GaN-on-sapphire layers for power electronics applications 用于电力电子应用的低氮掺杂MOCVD gan -on-蓝宝石层的物理和电气特性

Power electronic devices and components Pub Date : 2025-05-24 DOI: 10.1016/j.pedc.2025.100100

Ndembi Ignoumba-Ignoumba , Camille Sonneville , Adrien Bidaud , Pierre Brosselard , Eric Frayssinet , Florian Bartoli , Yvon Cordier , Farid Medjdoub , Dominique Planson , Cyril Buttay

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Optimization of the buffer layer in a 15kV SiC N-type gate commutated thyristor for safe, low-loss switching 用于安全低损耗开关的15kV SiC n型栅整流晶闸管缓冲层的优化

Power electronic devices and components Pub Date : 2025-05-17 DOI: 10.1016/j.pedc.2025.100099

Qinze Cao , Neophytos Lophitis , Arne Benjamin Renz , Kyrylo Melnyk , Marina Antoniou , Peter Michael Gammon

{"title":"Optimization of the buffer layer in a 15kV SiC N-type gate commutated thyristor for safe, low-loss switching","authors":"Qinze Cao , Neophytos Lophitis , Arne Benjamin Renz , Kyrylo Melnyk , Marina Antoniou , Peter Michael Gammon","doi":"10.1016/j.pedc.2025.100099","DOIUrl":"10.1016/j.pedc.2025.100099","url":null,"abstract":"<div><div>This paper explores the design and optimization of the buffer layer in Silicon Carbide (SiC) N-type Gate Commutated Thyristors (GCTs) to enhance low-loss switching and ensure safe operation in ultra high-voltage (over 10 kV) applications. The challenges posed by high dv/dt conditions during turn-off are known to cause snappy behaviour and high reverse current spikes through the cathode, which degrades switching reliability. Using Synopsys Technology Computer Aided Design (TCAD) models, validated against experimental data, the impact of the device design on the switching performance is investigated. By employing a carefully calibrated three-stage buffer design, we significantly reduce the high dv/dt which in turn is shown to alleviate the reverse cathode current caused by snap off effect. Furthermore, switching losses are reduced without substantially impacting the blocking voltage or the on-state voltage drop. Comparing the performance of the proposed design with conventional single buffer designs, the new GCT design demonstrates improved performance in terms of dv/dt control and energy loss during IGCT turn-off (31.8 % and 33.6 % respectively), in exchange for a 3.06 % increase in conduction losses. The results confirm that our proposed ”3-step buffer” design not only suppresses the snap off phenomenon but also extends the applicability of SiC IGCTs to broader high-power switching applications.</div></div>","PeriodicalId":74483,"journal":{"name":"Power electronic devices and components","volume":"11 ","pages":"Article 100099"},"PeriodicalIF":0.0,"publicationDate":"2025-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144124955","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Analysis of a novel packaging technique for natural voltage balancing of series-connected SiC-MOSFETs 一种新型串联sic - mosfet自然电压平衡封装技术分析

Power electronic devices and components Pub Date : 2025-05-15 DOI: 10.1016/j.pedc.2025.100097

Luciano F.S. Alves, Pierre Lefranc, Jean-Christophe Crebier, Pierre-Olivier Jeannin, Benoit Sarrazin

{"title":"Analysis of a novel packaging technique for natural voltage balancing of series-connected SiC-MOSFETs","authors":"Luciano F.S. Alves, Pierre Lefranc, Jean-Christophe Crebier, Pierre-Olivier Jeannin, Benoit Sarrazin","doi":"10.1016/j.pedc.2025.100097","DOIUrl":"10.1016/j.pedc.2025.100097","url":null,"abstract":"<div><div>This paper analyzes a novel packaging technique to improve the voltage-sharing performances of series-connected SiC-MOSFETs. The proposed method takes advantage of the parasitic capacitance network introduced by the packaging dielectric isolation layers to reduce the voltage imbalance across the series-connected devices. Firstly, the study carried out in this work explains how the parasitic capacitance networks introduced by the classic planar packaging and the gate drive circuits cause voltage imbalances across the devices. Therefore, a new packaging concept is analyzed to compensate for the effects of the gate driver parasitic capacitances. The concept is introduced and analyzed using equivalent models and mathematical approaches. To verify the analysis, the voltage sharing between two series-connected 1.2 kV SiC-MOSFETs is tested in a pulse test setup. The experimental results confirm that the proposed voltage-balancing technique can drastically improve the voltage-sharing performance of series-connected devices.</div></div>","PeriodicalId":74483,"journal":{"name":"Power electronic devices and components","volume":"11 ","pages":"Article 100097"},"PeriodicalIF":0.0,"publicationDate":"2025-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144105980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0