Power electronic devices and components最新文献

Evaluating current sensing methods for accurate characterization in small chip size SiC MOSFETs 评估在小片尺寸SiC mosfet中精确表征的电流传感方法

Power electronic devices and components Pub Date : 2025-06-01 DOI: 10.1016/j.pedc.2025.100102

Y. Kim, H. Park, S. Yoon, H. Kang

引用次数: 0

Physical and electrical characterizations of low n-doped MOCVD GaN-on-sapphire layers for power electronics applications 用于电力电子应用的低氮掺杂MOCVD gan -on-蓝宝石层的物理和电气特性

Power electronic devices and components Pub Date : 2025-05-24 DOI: 10.1016/j.pedc.2025.100100

Ndembi Ignoumba-Ignoumba , Camille Sonneville , Adrien Bidaud , Pierre Brosselard , Eric Frayssinet , Florian Bartoli , Yvon Cordier , Farid Medjdoub , Dominique Planson , Cyril Buttay

引用次数: 0

Optimization of the buffer layer in a 15kV SiC N-type gate commutated thyristor for safe, low-loss switching 用于安全低损耗开关的15kV SiC n型栅整流晶闸管缓冲层的优化

Power electronic devices and components Pub Date : 2025-05-17 DOI: 10.1016/j.pedc.2025.100099

Qinze Cao , Neophytos Lophitis , Arne Benjamin Renz , Kyrylo Melnyk , Marina Antoniou , Peter Michael Gammon

{"title":"Optimization of the buffer layer in a 15kV SiC N-type gate commutated thyristor for safe, low-loss switching","authors":"Qinze Cao , Neophytos Lophitis , Arne Benjamin Renz , Kyrylo Melnyk , Marina Antoniou , Peter Michael Gammon","doi":"10.1016/j.pedc.2025.100099","DOIUrl":"10.1016/j.pedc.2025.100099","url":null,"abstract":"<div><div>This paper explores the design and optimization of the buffer layer in Silicon Carbide (SiC) N-type Gate Commutated Thyristors (GCTs) to enhance low-loss switching and ensure safe operation in ultra high-voltage (over 10 kV) applications. The challenges posed by high dv/dt conditions during turn-off are known to cause snappy behaviour and high reverse current spikes through the cathode, which degrades switching reliability. Using Synopsys Technology Computer Aided Design (TCAD) models, validated against experimental data, the impact of the device design on the switching performance is investigated. By employing a carefully calibrated three-stage buffer design, we significantly reduce the high dv/dt which in turn is shown to alleviate the reverse cathode current caused by snap off effect. Furthermore, switching losses are reduced without substantially impacting the blocking voltage or the on-state voltage drop. Comparing the performance of the proposed design with conventional single buffer designs, the new GCT design demonstrates improved performance in terms of dv/dt control and energy loss during IGCT turn-off (31.8 % and 33.6 % respectively), in exchange for a 3.06 % increase in conduction losses. The results confirm that our proposed ”3-step buffer” design not only suppresses the snap off phenomenon but also extends the applicability of SiC IGCTs to broader high-power switching applications.</div></div>","PeriodicalId":74483,"journal":{"name":"Power electronic devices and components","volume":"11 ","pages":"Article 100099"},"PeriodicalIF":0.0,"publicationDate":"2025-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144124955","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Analysis of a novel packaging technique for natural voltage balancing of series-connected SiC-MOSFETs 一种新型串联sic - mosfet自然电压平衡封装技术分析

Power electronic devices and components Pub Date : 2025-05-15 DOI: 10.1016/j.pedc.2025.100097

Luciano F.S. Alves, Pierre Lefranc, Jean-Christophe Crebier, Pierre-Olivier Jeannin, Benoit Sarrazin

{"title":"Analysis of a novel packaging technique for natural voltage balancing of series-connected SiC-MOSFETs","authors":"Luciano F.S. Alves, Pierre Lefranc, Jean-Christophe Crebier, Pierre-Olivier Jeannin, Benoit Sarrazin","doi":"10.1016/j.pedc.2025.100097","DOIUrl":"10.1016/j.pedc.2025.100097","url":null,"abstract":"<div><div>This paper analyzes a novel packaging technique to improve the voltage-sharing performances of series-connected SiC-MOSFETs. The proposed method takes advantage of the parasitic capacitance network introduced by the packaging dielectric isolation layers to reduce the voltage imbalance across the series-connected devices. Firstly, the study carried out in this work explains how the parasitic capacitance networks introduced by the classic planar packaging and the gate drive circuits cause voltage imbalances across the devices. Therefore, a new packaging concept is analyzed to compensate for the effects of the gate driver parasitic capacitances. The concept is introduced and analyzed using equivalent models and mathematical approaches. To verify the analysis, the voltage sharing between two series-connected 1.2 kV SiC-MOSFETs is tested in a pulse test setup. The experimental results confirm that the proposed voltage-balancing technique can drastically improve the voltage-sharing performance of series-connected devices.</div></div>","PeriodicalId":74483,"journal":{"name":"Power electronic devices and components","volume":"11 ","pages":"Article 100097"},"PeriodicalIF":0.0,"publicationDate":"2025-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144105980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Impact of voids on the solder joint integrity and fatigue life of IGBT power module 空隙对IGBT电源模块焊点完整性和疲劳寿命的影响

Power electronic devices and components Pub Date : 2025-05-15 DOI: 10.1016/j.pedc.2025.100098

Sunday E. Nebo, Emeka H. Amalu, David J. Hughes

{"title":"Impact of voids on the solder joint integrity and fatigue life of IGBT power module","authors":"Sunday E. Nebo, Emeka H. Amalu, David J. Hughes","doi":"10.1016/j.pedc.2025.100098","DOIUrl":"10.1016/j.pedc.2025.100098","url":null,"abstract":"<div><div>Insulated gate bipolar transistor (IGBT) power module is a key component of actuator devices in many systems which include electric vehicles (EVs). However, as the deployment of IGBT modules penetrates several mission-critical systems operating in harsher ambient, process voids in the solder joints challenge their reliability and fatigue life. This investigation quantifies the impact of presence of 10% voids in critical solder joints on the integrity and fatigue-life of IGBT module for reliable field operation. Computational modelling utilising python programming algorithm deployed in Monte-Carlo technique is used to generate realist distributions of spatial random voids on three representative volume elements (RVEs) of critical solder joints in three IGBT modules. The three modules have elliptical voids, spherical voids and a combination of elliptical and spherical voids, respectively. A fourth control module has no void. Solder joints in the models comprises 96.5% tin, 3.0% silver, and 0.5% copper (SAC305). The IEC 60068-2-14 temperature load cycle and Anand’s visco-plastic model are employed as the load and constitutive model, respectively. Other component materials are modelled with appropriate time and temperature dependent models and material properties. Combined elliptical and spherical voids induced the highest damage while elliptical voids induced the highest plastic strain of 0.045 µm/µm magnitude in the joints. Accumulated stress and strain energy have magnitudes of 74.05 MPa and 2.63 × 10<sup>5</sup> pJ, respectively. Ten percent elliptical voids in the joints reduced the fatigue life of the module by 59.5%.</div></div>","PeriodicalId":74483,"journal":{"name":"Power electronic devices and components","volume":"11 ","pages":"Article 100098"},"PeriodicalIF":0.0,"publicationDate":"2025-05-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144106058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Construction and electrical properties of 700 V aluminium polymer electrolytic capacitors 700 V聚合物铝电解电容器的结构和电性能

Power electronic devices and components Pub Date : 2025-05-03 DOI: 10.1016/j.pedc.2025.100096

Tim Kruse , Luciana Tavares , Ulrich Schürmann , Lorenz Kienle , Thomas Ebel

{"title":"Construction and electrical properties of 700 V aluminium polymer electrolytic capacitors","authors":"Tim Kruse , Luciana Tavares , Ulrich Schürmann , Lorenz Kienle , Thomas Ebel","doi":"10.1016/j.pedc.2025.100096","DOIUrl":"10.1016/j.pedc.2025.100096","url":null,"abstract":"<div><div>A process for the construction of a high voltage aluminium polymer electrolytic capacitor with operation voltages of up to 700 V is presented in this paper. Thin 150 <span><math><mi>μ</mi></math></span>m, high purity aluminium films are anodized at a constant voltage with various anodization steps in a dilute boric acid solution to voltages between 1000 V and 1500 V. Single capacitor stacks were built, using the anodized aluminium, commercial cathode foils, paper separator and a PEDOT:PSS electrolyte. The resulting capacitors were electrically characterized by their capacitance, equivalent series resistance, breakdown voltage, and leakage current. Capacitance measurements showed that the thickness of the oxide film grew linearly with the forming voltage. The breakdown voltage exhibits a saturation behaviour with rising forming voltages, meaning that thicker oxide grown at voltages higher than 1000 V does not lead to proportional higher breakdown voltages. Oxide investigations showed that many defects are present at the surface at the highest forming voltages. Cross sections showed that the oxide underneath these defects have many voids that presumably lead to an earlier breakdown. Nonetheless, at a forming voltage of 1500 V, the breakdown voltage of the capacitor cells is at an average of 789 V with some samples going up to 800 V, which is more than three times the rated voltage of state-of-the-art devices.</div></div>","PeriodicalId":74483,"journal":{"name":"Power electronic devices and components","volume":"11 ","pages":"Article 100096"},"PeriodicalIF":0.0,"publicationDate":"2025-05-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143908240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Low leakage and high blocking voltage GaN-on-GaN Schottky diode by TMAH surface treatment 低漏高阻电压GaN-on-GaN肖特基二极管的TMAH表面处理

Power electronic devices and components Pub Date : 2025-04-23 DOI: 10.1016/j.pedc.2025.100092

Vishwajeet Maurya , Daniel Alquier , Hala El Rammouz , Pedro Fernandes Paes Pinto Rocha , Thomas Kaltsounis , Eugénie Martinez , Florian Bartoli , Eric Frayssinet , Yvon Cordier , Matthew Charles , Julien Buckley

引用次数: 0

GaN half-bridges on electrical and thermal co-designed ceramic substrates 在电和热共同设计的陶瓷衬底上的氮化镓半桥

Power electronic devices and components Pub Date : 2025-04-17 DOI: 10.1016/j.pedc.2025.100091

Manuel Rueß , Peter Mack , Dominik Koch , Aline Reck , Mathias C.J. Weiser , André Zimmermann , Ingmar Kallfass

{"title":"GaN half-bridges on electrical and thermal co-designed ceramic substrates","authors":"Manuel Rueß , Peter Mack , Dominik Koch , Aline Reck , Mathias C.J. Weiser , André Zimmermann , Ingmar Kallfass","doi":"10.1016/j.pedc.2025.100091","DOIUrl":"10.1016/j.pedc.2025.100091","url":null,"abstract":"<div><div>This work presents an analysis of an electrically and thermally optimized GaN half-bridge module based on ceramic a substrate. An effective thermal and electrical co-design is a decisive factor in achieving high efficiency and power density. In order to utilize the advantages of both GaN for high switching frequencies and ceramic substrates for excellent thermal properties, an electrical and thermal co-designed substrate stack-up for MHz applications is presented. This stack-up features a <span><math><mrow><mn>40</mn><mspace></mspace><mi>μ</mi></mrow></math></span>m thin ceramic layer resulting in a measured power loop inductance of <span><math><mrow><msub><mrow><mi>L</mi></mrow><mrow><mtext>loop,VNA</mtext></mrow></msub><mo>=</mo><mn>489</mn><mspace></mspace><mstyle><mi>p</mi><mi>H</mi></mstyle></mrow></math></span> and a ceramic carrier for an electrically isolated and thermally optimized connection to the heat sink. In a 48V to 24V buck converter switching at frequencies of up to 2 MHz, a difference in efficiency of 1% is achieved compared to a electrically enhanced rigid-flex substrate using a <span><math><mrow><mn>25</mn><mspace></mspace><mi>μ</mi></mrow></math></span>m polyimide layer. At a switching frequency of 500kHz, a power density of <span><math><mrow><mn>1</mn><mspace></mspace><msup><mrow><mtext>kW/cm</mtext></mrow><mrow><mn>3</mn></mrow></msup></mrow></math></span> is achieved with an efficiency of over 95%, accompanied by the possibility of significantly improving the thermal resistance with an all-ceramic stack-up, which enables GaN half-bridges with high frequencies and power densities.</div></div>","PeriodicalId":74483,"journal":{"name":"Power electronic devices and components","volume":"11 ","pages":"Article 100091"},"PeriodicalIF":0.0,"publicationDate":"2025-04-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143879310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Design and performance evaluation of low-voltage solid-state DCCB using capacitor-based surge mitigation techniques 使用基于电容的浪涌缓解技术的低压固态DCCB的设计和性能评估

Power electronic devices and components Pub Date : 2025-04-16 DOI: 10.1016/j.pedc.2025.100095

Mehdi Moradian , Tek Tjing Lie , Kosala Gunawardane

{"title":"Design and performance evaluation of low-voltage solid-state DCCB using capacitor-based surge mitigation techniques","authors":"Mehdi Moradian , Tek Tjing Lie , Kosala Gunawardane","doi":"10.1016/j.pedc.2025.100095","DOIUrl":"10.1016/j.pedc.2025.100095","url":null,"abstract":"<div><div>This article conducts practical tests on four different configurations of solid-state DC circuit breakers (SS-DCCBs), investigating fault detection and circuit interruption phenomena in DC systems. It analyses circuit formulations and design principles, compares the topologies, and evaluates results. Since all circuit operation results are considered acceptable, the article scrutinizes circuit configurations and selects the most effective surge absorption technique based on active and passive components and surge mitigation complexity. The primary switch in the proposed models is a MOSFET, while the bypass switches are IGBT and Thyristor. The traditional surge absorption method using Metal Oxide Varistor (MOV) is contrasted with three topologies employing the capacitor current block technique (CBT). Practical testing and discussion of the effects of circuit inductance on switching speed and operation are also included. Real-world modeling incorporating inductance on both the line and load sides is utilized throughout all experiments to assess realistic outcomes. The optimal surge absorption configuration will be chosen based on its ability to meet various criteria, including efficient operation, rapid response, minimal complexity on both power and control sides, and the involvement of active and passive components. The tests were carried out on a system with a <em>48</em> V DC supply.</div></div>","PeriodicalId":74483,"journal":{"name":"Power electronic devices and components","volume":"11 ","pages":"Article 100095"},"PeriodicalIF":0.0,"publicationDate":"2025-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143844970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Monolithic integration of circuits in e-mode GaN HEMT technology 电子模GaN HEMT技术中电路的单片集成

Power electronic devices and components Pub Date : 2025-04-09 DOI: 10.1016/j.pedc.2025.100089

Plinio Bau, Thanh Hai Phung, Stephane Driussi, Thomas Beauchene

引用次数: 0