2019 IEEE 69th Electronic Components and Technology Conference (ECTC)最新文献

{"title":"Construction of FO-MCM with C4 Bumps Built First Using Chip Last Assembly Technology","authors":"Chih-Hsun Hsu, Wen-Yang Li, Chi‐Jen Chen, Y. Jiang, Jui-Feng Tai, Chang-Fu Lin, C. Chung","doi":"10.1109/ECTC.2019.00009","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00009","url":null,"abstract":"Chip last assembly technology is complex and higher cost for fan-out wafer level package (FOWLP). But, this technology is fit well for very high density interconnection packages. This article presents chip last assembly technology using C4 bump-first for fan out multi-chip module (FO-MCM) package. The objective is to reduce cycle-time. A chip module with 28 x 30 mm was fabricated using 2 daisy-chain Si dies that bonded onto 2/2 µm line/space redistribution layers (RDLs). This module was then assembled on high density substrate with size of 70 x 70 mm. This FOMCM package is constructed using C4 first process. C4 bumps were built on same side of the carrier after RDL was fabricated. The assemblies were protected and bonded on the carrier using temporary bond glue. The 1st carrier was then de-bonded. High I/O Si dies were attached onto the opposite side of the carrier followed by molding. The difference between C4 first and C4 last is the Si dies that were attached and molded with the carrier first then fabricated the C4 bumps. C4 first process has the challenge is micro-pads pattern shift between Si dies. By increasing the RDL density, one could reduce the irregular of micro-pads pattern shift. Additionally, by reducing the thermal budget and using higher Tg of the temporary bond glue, the pattern shift was improved to less than 5 mm. Additionally, the wafer warpage of C4 first was found consistently warped at the same side, thus the process was easier to control as compared to C4 last. The assembled FOMCM packages were then stressed for reliability tests. It passed 1000 hours of high temperature storage life test; MSL4 preconditioning with 1000 thermal cycles under B-conditions (-55~125 °C) and 192 hours unbiased high accelerated stress. Details of the results will be presented and discussed.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"30 1","pages":"7-13"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85899955","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Silver Sintering on Organic Substrates for the Embedding of Power Semiconductor Devices","authors":"A. Schiffmacher, J. Wilde, Lorenz Litzenberger, T. Huesgen, V. Polezhaev","doi":"10.1109/ECTC.2019.00222","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00222","url":null,"abstract":"The requirements for power electronic assemblies are continuously increasing and are mainly driven by costs, functionality, and reliability. A novel and promising approach is the embedding of power semiconductor devices into PCB-materials. Benefits are the reduction in size and volume of the system. The embedding of semiconductor devices provides a high degree of miniaturization. Also printed circuit board technology in combination with the use of established processes apparently has the potential for low-cost manufacturing. Further functional advantages are the possibility to place passive components and peripheral circuits close to the switching devices, enabling shorter commutating paths. In consequence, they are expected to produce smaller parasitic effects caused by the package, which results in higher possible frequencies and reduced conduction and switching losses. However, there is a significant challenge regarding package design, processing, and materials selection to make use of this potential even at high operating temperatures. To address only one aspect, generally used materials, like epoxy-glass-substrates (FR4) and solder alloys like PbSnAg or SAC are not suitable for temperatures above 150 °C. This work will introduce and evaluate a concept for double-side Ag-sintered semiconductor chips, which are embedded between two organic high-temperature PCBs. A proof-of-concept will be presented by setting up a 30 kW (600 V, 50 A) power package as a demonstrator.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"20 1","pages":"1443-1450"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76496426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"3D-MiM (MUST-in-MUST) Technology for Advanced System Integration","authors":"A. Su, T. Ku, C. Tsai, K. Yee, Douglas C. H. Yu","doi":"10.1109/ECTC.2019.00008","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00008","url":null,"abstract":"An advanced 3D Multi-stack (MUST) system integration technology, 3D MUST-in-MUST (3D-MiM) fan out package, has been developed as next generation wafer-level fan-out package technology. 3D-MiM technology utilizes a more simplified architecture which eliminates BGAs between packages for system-level performance, power and form-factor (PPA) purpose. This technology also makes use of a modularized approach for both design and integration flow to improve design flexibility and integration efficiency. Known-good pre-stacked memory cube and/or logic-memory cubes are fabricated by leveraging the established integrated fan-out technology platform (InFO) in tools, materials, design rules, and processes to shorten development cycle time and achieve cost effectiveness. Two 3D-MiM fan-out examples are presented in this paper. The first 3D-MiM package integrates a SoC with 16 memory chips in a 15x15 mm2 footprint with 0.5 mm package height (final BGA included) for mobile application. The other 3D-MiM package integrates 8 SoCs with 32 memory chips in a 43x28 mm2 footprint to mimic a system integration of multiple logic cores and multiple memory chips for HPC applications.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"69 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86907303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Feasibility Study of Fan-Out Panel-Level Packaging for Heterogeneous Integrations","authors":"C. Ko, Henry Yang, J. Lau, Ming Li, Curry Lin, Chieh-Lin Chang, Jhih-Yuan Pan, Hsing-Hui Wu, Iris Xu, Tony Chen, Zhang Li, K. Tan, Penny Lo, R. So, Y. H. Chen, N. Fan, E. Kuah, M. Lin, Y. Cheung, Eric Ng, Cao Xi, R. Beica, S. Lim, N. Lee, Mian Tao, J. Lo, Ricky S. W. Lee","doi":"10.1109/ECTC.2019.00010","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00010","url":null,"abstract":"The design, materials, process, and fabrication of a heterogeneous integration of 4 chips by a FOPLP (fan-out panel-level packaging) with chip-first and dies face-down formation are investigated in this study. Emphasis is placed on the application of a new assembly process and materials for fabricating the RDLs (redistribution layers) of the FOPLP. The panel size is 508mm x 508mm. The epoxy molding compound (EMC) is a dry-film material and is molded by lamination method. The minimum metal line width and spacing is 10µm and they are fabricated by printed circuit board (PCB) method and equipment.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"16 1","pages":"14-20"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87302634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Fine-Pitch (≤10 µm) Direct Cu-Cu Interconnects Using In-Situ Formic Acid Vapor Treatment","authors":"SivaChandra Jangam, A. Bajwa, U. Mogera, Pranav Ambhore, Tom Colosimo, B. Chylak, S. Iyer","doi":"10.1109/ECTC.2019.00099","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00099","url":null,"abstract":"We demonstrate a solderless direct copper-copper (Cu-Cu) thermal compression bonding (TCB) process for die-to-wafer assembly in ambient environment using a novel in-situ formic acid vapor treatment. We show that this approach produces excellent Cu-Cu bonds with an average shear strength of >150 MPa. Using this TCB process, we demonstrate dielet assemblies on the Silicon-Interconnect Fabric (Si-IF) platform with fine-pitch (≤ 10 µm) Cu-Cu interconnects. Further, we show electrical continuity across multiple dies on the Si-IF with an interconnect specific contact resistance of <0.7 Ω-µm2.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"75 1","pages":"620-627"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86006735","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Reliability Investigation of Extremely Large Ratio Fan-Out Wafer-Level Package with Low Ball Density for Ultra-Short-Range Radar","authors":"P.S. Huang, C.K. Yu, W. S. Chiang, M. Z. Lin, Y.H. Fang, M. J. Lin, N. Liu, B. Lin, I. Hsu","doi":"10.1109/ECTC.2019.00081","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00081","url":null,"abstract":"Driven by aggressive development of electronic products with high robustness demand for automotive application to endure severe usage environment, both component-level and board-level reliabilities have to be concerned more for safety assurance. In this paper, a system-on-chip millimeter-wave ultra-short range radar (mmWave USRR) realized in complementary metal-oxide-semiconductor (CMOS) technology and assembled with fan-out wafer level packaging (FOWLP) technology was introduced, and the board-level reliability (BLR) was studied experimentally on the risk of chip-to-board interaction (CBI). The factors of solder ball material, package thickness and underfill material, thought to dominate on CBI performance, were studied experimentally. First of all, two solder materials were studied to evaluate their capabilities for this FOWLP to against board level thermal cycling and drop tests. It was found that the solder with higher elastic modulus performed much better on board-level thermal cycling (BLTC) reliability. Moreover, no difference was found in board level drop test since no failure occurred in both solder materials. Both package thicknesses of 425 µm and 580 µm were studied on the board level reliabilities, and the results revealed that the design with both thicker Si die and thicker molding material significantly improved the BLTC reliability. Both epoxy-based materials - one is low-CTE underfill material and the other is edge-bond glue, were applied to know the workability of enhancing the BLTC performance on the FOWLP. The experiment results showed that both the epoxy materials miserably decreased the BLTC performance, and severe solder crack and bulk underfill crack were found. Since vibration test is indispensable and of much concern for automotive electronics, the stringent test condition of sine-wave frequency swept from 20 Hz to 2,000 Hz and peak acceleration of either 50g or 20g, was applied to evaluate anti-vibration property of the FOWLP mTV mounted on daisy-chain PCB. From the results of 50g peak acceleration vibration test, high resistance was found in the specific daisy-chain loop which electrically connects corner solder balls. From the failure analysis it could be found that delamination existed at the interface of redistribution layer (RDL) and under-bump metallization (UBM) of component side and PCB Cu trace crack. It is noteworthy that all the failures only happened on the package located at the 5x3 array corner while subjecting to Z-axis vibration. From experience, poorly fixing the PCB on vibration platform potentially causes more bending stain on PCB during Z-direction vibration and further concentrates much higher stress singularly nearby the corner. Moreover, the board-level vibration test with 20g peak acceleration was also implemented, and there wasn't any failure found. Finally, the BLR was thoroughly studied for the extremely large area-ratio FOWLP, and the package was proved its capability of meeting AEC-Q100 compl","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"25 1","pages":"493-497"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87516626","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A New Development of Direct Bonding to Aluminum and Nickel Surfaces by Silver Sintering in air Atmosphere","authors":"Ly May Chew, Tamira Stegmann, Erika Schwenk, M. Dubis, W. Schmitt","doi":"10.1109/ECTC.2019.00021","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00021","url":null,"abstract":"Owing to the superb properties of silver such as high melting temperature, high thermal and electrical conductivity, low temperature silver sinter technology has attracted growing attention in recent years especially for the applications required high power and high operating temperature. Current silver sinter technology required plating of precious metal finishing on the substrates prior to sintering process in order to form a strong sinter joint. Direct bonding on non-precious metal surfaces by silver sintering is therefore of great interest, since the precious metal finishing on substrate is no longer necessary, which will lead to the reduction of manufacturing cost. This paper explores the development of a safe-to-use micro-silver sinter paste for pressure sintering on aluminum and nickel surfaces. In this study, Ag metallized Si dies were attached on nickel-plated direct copper bonding substrates and high purity aluminum plates by silver sintering process at 250 °C with a pressure of 10 MPa for 3 min in air atmosphere. The cross-sectional SEM images of sintered samples indicate that a dense sintered layer was formed on Ni and Al surface. After die shear test, SEM-EDX was conducted on the fracture surface of Ni and Al substrates and the results confirmed that silver sintered joint was created on Ni and Al surface. The EDX analysis results further illustrate an interdiffusion of Ag/Ni and Ag/Al occurred at the interface located between sintered layer and substrates. High bonding strength of silver sintered joint was created on Ni and Al surfaces and the average die shear strength remained above 30 N/mm² after 500 h storage at 250 °C. Cohesive break in the sintered layer was obtained for both Ni and Al samples before and after high temperature storage where silver sintered layer can be found on both the die backside and the substrate surface indicating that good adhesion on Ni and Al surfaces was achieved with the newly developed silver sinter paste.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"19 1","pages":"87-93"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72847118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Novel Solder Pads for Self-Aligned Flip-Chip Assembly","authors":"Y. Martin, S. Kamlapurkar, N. Marchack, J. Nah, T. Barwicz","doi":"10.1109/ECTC.2019.00086","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00086","url":null,"abstract":"Self-alignment via solder-surface tension in flip-chip bonding opens the door to low-cost, high-throughput assembly of components with sub-micron accuracy. This is especially impactful to integrated photonics as used for high speed optical communication and sensors [1,2]. Assembly yield hinges on the details of solder-induced forces and on the geometry of the melted solder surface. Low curvature of melted solder is best to balance solder forces for optimal re-alignment yield but leads to shallow contact angles and solder de-wetting on traditional solder pads. We introduce and demonstrate the concept of recessed solder pads with shallow angled edges. Such geometry enables arbitrarily-low curvature of the molten solder surface and even flat or slightly concave shapes. The solder stays anchored at the angled edges of recessed pads and can be made to flow in long and narrow conduits. Both aspects are key to widening the fabrication and process window for the solder-induced chip-alignment technology.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"78 1","pages":"528-534"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81185074","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Active Through-Silicon Interposer Based 2.5D IC Design, Fabrication, Assembly and Test","authors":"J. Jayabalan, V. C. Nachiappan, Sharon Lim Pei Siang, Wang Xiangyu, Jong Ming Chinq, S. Bhattacharya","doi":"10.1109/ECTC.2019.00094","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00094","url":null,"abstract":"Active Through-Silicon Interposer (ATSI) based 2.5D/3D IC packaging is a solution to extend Moore's law beyond the limitations inherent in 2D packages. We present the implementation of an ATSI platform for providing Analog to Digital converter (ADC), Digital to Analog converter (DAC) and embedded Power Management Unit (ePMU) functions to support high performance logic, fabrication of 140 micron pitch Via-Last Through-Silicon Via (TSV) of 40 micron height, assembly of Chip-on-Chip-on Substrate, functional test and reliability assessment. The active interposer fabricated in 130nm CMOS easily supports the I/O, Analog, Electro Static Discharge (ESD), De-cap functions with via-last TSV. This approach enables significant die-size reduction of the top die (usually in expensive 16nm CMOS or below tech. node) to achieve system miniaturization and cost reduction","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"108 1","pages":"587-593"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81624474","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Low Temperature Cu Interconnect with Chip to Wafer Hybrid Bonding","authors":"Guilian Gao, L. Mirkarimi, Thomas Workman, G. Fountain, J. Theil, Gabe Guevara, Ping Liu, Bongsub Lee, P. Mrozek, M. Huynh, C. Rudolph, T. Werner, A. Hanisch","doi":"10.1109/ECTC.2019.00100","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00100","url":null,"abstract":"Current DRAM advanced chip stack packages such as the high bandwidth memory (HBM) use throughsilicon-via (TSV) and thermal compression bonding (TCB) of solder capped micro bumps for the inter-layer connection. The bonding process has low throughput and cannot overcome the challenge of scaling below 40 µm pitch. These are compelling reasons to seek an alternative approach such as hybrid bonding. The pursuit of fine pitch die stacking with TSV interconnect using hybrid bonding is pervasive in the packaging industry today due to the promise of improved performance. Specifically, the Cu interconnect provides improved thermal and electrical performance and the all inorganic interface of the complete die stack offers enhanced thermal-mechanical performance and reliability in the final chip stack. Direct Bond Interconnect technology, also known as low temperature hybrid bonding, forms a spontaneous dielectric-to-dielectric bond at room temperature and then establishes metal-to-metal connection (usually Cu-to-Cu bond) by a low temperature batch annealing process (150 – 300°C). The direct bond process eliminates the need for solder and underfill and associated problems. While the hybrid bonding exists today in wafer-towafer (W2W) format in high volume manufacturing, chip to wafer (C2W) bonding developed for future product lines is making significant process in the past three years. A bonding process with high throughput has been demonstrated with electrical test yield above 90% with a daisy chain structure that covers 50mm^2 of bonding area. The bonded parts showed superior reliability performance in temperature cycling, high temperature storage and autoclave testing. This paper presents the latest development in C2W hybrid bonding and demonstrates the low temperature annealing capability and integration with TSV.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"61 1","pages":"628-635"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91100824","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}