基于有源通硅中间体的2.5D集成电路设计、制造、组装和测试

J. Jayabalan, V. C. Nachiappan, Sharon Lim Pei Siang, Wang Xiangyu, Jong Ming Chinq, S. Bhattacharya
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引用次数: 9

摘要

基于有源通硅中间体(ATSI)的2.5D/3D IC封装是一种扩展摩尔定律的解决方案,超越了2D封装固有的限制。我们提出了一个ATSI平台的实现,提供模数转换器(ADC),数模转换器(DAC)和嵌入式电源管理单元(ePMU)功能,以支持高性能逻辑,制造140微米间距的40微米高度的通硅通孔(TSV),片上片基板组装,功能测试和可靠性评估。采用130nm CMOS制造的有源中间体可轻松支持I/O、模拟、静电放电(ESD)、De-cap等功能。这种方法可以显著减小顶晶片(通常采用昂贵的16nm CMOS或以下技术节点)的晶片尺寸,从而实现系统小型化和降低成本
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Active Through-Silicon Interposer Based 2.5D IC Design, Fabrication, Assembly and Test
Active Through-Silicon Interposer (ATSI) based 2.5D/3D IC packaging is a solution to extend Moore's law beyond the limitations inherent in 2D packages. We present the implementation of an ATSI platform for providing Analog to Digital converter (ADC), Digital to Analog converter (DAC) and embedded Power Management Unit (ePMU) functions to support high performance logic, fabrication of 140 micron pitch Via-Last Through-Silicon Via (TSV) of 40 micron height, assembly of Chip-on-Chip-on Substrate, functional test and reliability assessment. The active interposer fabricated in 130nm CMOS easily supports the I/O, Analog, Electro Static Discharge (ESD), De-cap functions with via-last TSV. This approach enables significant die-size reduction of the top die (usually in expensive 16nm CMOS or below tech. node) to achieve system miniaturization and cost reduction
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