2019 IEEE 69th Electronic Components and Technology Conference (ECTC)最新文献_第5页

A MEMS Microphone in a FOWLP FOWLP中的MEMS麦克风

2019 IEEE 69th Electronic Components and Technology Conference (ECTC) Pub Date : 2019-05-28 DOI: 10.1109/ECTC.2019.00134

H. Theuss, C. Geissler, Franz-Xaver Muehlbauer, Claus von Waechter, T. Kilger, J. Wagner, T. Fischer, U. Bartl, Stephan Helbig, A. Sigl, D. Maier, B. Goller, Matthias Vobl, M. Herrmann, J. Lodermeyer, U. Krumbein, A. Dehé

引用次数: 7

Cu Pillar with Nanocopper Caps: The Next Interconnection Node Beyond Traditional Cu Pillar 纳米铜帽铜柱:超越传统铜柱的下一个互连节点

2019 IEEE 69th Electronic Components and Technology Conference (ECTC) Pub Date : 2019-05-28 DOI: 10.1109/ECTC.2019.00104

Ramón A. Sosa, K. Mohan, L. Nguyen, R. Tummala, A. Antoniou, V. Smet

{"title":"Cu Pillar with Nanocopper Caps: The Next Interconnection Node Beyond Traditional Cu Pillar","authors":"Ramón A. Sosa, K. Mohan, L. Nguyen, R. Tummala, A. Antoniou, V. Smet","doi":"10.1109/ECTC.2019.00104","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00104","url":null,"abstract":"Off-chip interconnection pitch scaling has been aggressively driven over the last several decades by the continuous need for higher bandwidth and computing power in smaller form factors in emerging high-performance computing systems. It is expected to reach below 10µm I/O pitch in the near future, beyond the fundamental limits of traditional solder-based interconnection technologies. While the Cu pillar with solder caps technology remains attractive in chip-to-substrate (C2S) applications as it can accommodate substrate and chip non-coplanarities during assembly through melting of the solder, all-Cu interconnections are now pursued as the next interconnection node for their pitch and performance scalability. However, direct Cu-Cu bonding faces several key challenges that have hindered large-scale adoption in C2S, including its relatively high elastic modulus, giving low compliance in assembly. To address this challenge, a novel interconnection technology - Cu pillar with nanocopper caps - is proposed where a solid-state sub-20 GPa modulus nanoporous Cu cap is introduced to replace the solder cap and retain solder-like compliance in assembly, while achieving bulk-like properties through densification in low-temperature sintering. This paper presents the design of this new interconnection system, the developed wafer bumping process, compatible with current industry infrastructures, and a first assembly demonstration where a seamless interface was achieved.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"2 1","pages":"655-660"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88413418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Solder Joint Reliability of Double-Side Mounted DDR Modules for Consumer and Automotive Applications 消费类和汽车应用的双面安装DDR模块的焊点可靠性

2019 IEEE 69th Electronic Components and Technology Conference (ECTC) Pub Date : 2019-05-28 DOI: 10.1109/ECTC.2019.00080

Dongji Xie, Joe Hai, Zhongming Wu, M. Economou

引用次数: 2

Construction of FO-MCM with C4 Bumps Built First Using Chip Last Assembly Technology 采用片末组装技术构建C4凸块的FO-MCM

2019 IEEE 69th Electronic Components and Technology Conference (ECTC) Pub Date : 2019-05-28 DOI: 10.1109/ECTC.2019.00009

Chih-Hsun Hsu, Wen-Yang Li, Chi‐Jen Chen, Y. Jiang, Jui-Feng Tai, Chang-Fu Lin, C. Chung

{"title":"Construction of FO-MCM with C4 Bumps Built First Using Chip Last Assembly Technology","authors":"Chih-Hsun Hsu, Wen-Yang Li, Chi‐Jen Chen, Y. Jiang, Jui-Feng Tai, Chang-Fu Lin, C. Chung","doi":"10.1109/ECTC.2019.00009","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00009","url":null,"abstract":"Chip last assembly technology is complex and higher cost for fan-out wafer level package (FOWLP). But, this technology is fit well for very high density interconnection packages. This article presents chip last assembly technology using C4 bump-first for fan out multi-chip module (FO-MCM) package. The objective is to reduce cycle-time. A chip module with 28 x 30 mm was fabricated using 2 daisy-chain Si dies that bonded onto 2/2 µm line/space redistribution layers (RDLs). This module was then assembled on high density substrate with size of 70 x 70 mm. This FOMCM package is constructed using C4 first process. C4 bumps were built on same side of the carrier after RDL was fabricated. The assemblies were protected and bonded on the carrier using temporary bond glue. The 1st carrier was then de-bonded. High I/O Si dies were attached onto the opposite side of the carrier followed by molding. The difference between C4 first and C4 last is the Si dies that were attached and molded with the carrier first then fabricated the C4 bumps. C4 first process has the challenge is micro-pads pattern shift between Si dies. By increasing the RDL density, one could reduce the irregular of micro-pads pattern shift. Additionally, by reducing the thermal budget and using higher Tg of the temporary bond glue, the pattern shift was improved to less than 5 mm. Additionally, the wafer warpage of C4 first was found consistently warped at the same side, thus the process was easier to control as compared to C4 last. The assembled FOMCM packages were then stressed for reliability tests. It passed 1000 hours of high temperature storage life test; MSL4 preconditioning with 1000 thermal cycles under B-conditions (-55~125 °C) and 192 hours unbiased high accelerated stress. Details of the results will be presented and discussed.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"30 1","pages":"7-13"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85899955","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Room-Temperature Bonding with Pd Coated Cu Wire on Al Pads: Ball Bond Optimization with 2-Stage Methodology Al衬垫上Pd涂层铜线的室温键合:用两阶段方法优化球键合

2019 IEEE 69th Electronic Components and Technology Conference (ECTC) Pub Date : 2019-05-28 DOI: 10.1109/ECTC.2019.00-14

Nicholas Kam, M. Hook, Celal Con, K. Karim, M. Mayer

{"title":"Room-Temperature Bonding with Pd Coated Cu Wire on Al Pads: Ball Bond Optimization with 2-Stage Methodology","authors":"Nicholas Kam, M. Hook, Celal Con, K. Karim, M. Mayer","doi":"10.1109/ECTC.2019.00-14","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00-14","url":null,"abstract":"Wirebonding performed at elevated temperatures is the standard interconnect process for integrated circuits, typically with the use of low-cost copper bonding wire. However, for specific applications it is necessary for wire bonds to be reliably joined at room-temperature. This paper details the development of a room-temperature ball bonding process using a 2-stage optimization method. The first stage optimizes ball geometry by applying a 32 design of experiment to bonding parameters impact force (IF) and electric flame-off (EFO) current. In the second stage bond shear strength is optimized by stepwise increase in ultrasonic amplitude. Target ball bond values were attained at optimized parameters: IF of 1331 mN, EFO current of 59.9 mA, and an ultrasonic amplitude of 26.46 US%. Pad lift during bonding was observed at excessive ultrasonic amplitudes above 40 US%, as determined by optical images at the bond interface. Bonding parameters at room-temperature (23°C) were increased when compared to a high temperature process (175°C) to account for reduced thermal energy. For the same geometry at room-temperature a 7 % increase to impact force was required. EFO current levels remained relatively constant between the two bonding temperatures. For the same shear strength at room-temperature a 18 % increase in ultrasound amplitude was required. The confirmed average shear strength achieved via the room-temperature process was 116 MPa. Higher values are possible.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"4 1","pages":"2219-2224"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82629657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Active Interposer Technology for Chiplet-Based Advanced 3D System Architectures 基于芯片的先进3D系统架构的主动中介技术

2019 IEEE 69th Electronic Components and Technology Conference (ECTC) Pub Date : 2019-05-28 DOI: 10.1109/ECTC.2019.00092

P. Coudrain, J. Charbonnier, A. Garnier, P. Vivet, R. Vélard, A. Vinci, F. Ponthenier, A. Farcy, R. Segaud, P. Chausse, L. Arnaud, D. Lattard, E. Guthmuller, G. Romano, A. Gueugnot, F. Berger, J. Beltritti, T. Mourier, M. Gottardi, S. Minoret, C. Ribiére, G. Romero, Pierre-Emile Philip, Y. Exbrayat, D. Scevola, D. Campos, M. Argoud, N. Allouti, R. Eleouet, César Fuguet Tortolero, C. Aumont, D. Dutoit, Corinne Legalland, J. Michailos, S. Chéramy, G. Simon

引用次数: 37

The Thermal Dissipation Characteristics of The Novel System-In-Package Technology (ICE-SiP) for Mobile and 3D High-end Packages 用于移动和3D高端封装的新型系统级封装技术(ICE-SiP)的散热特性

2019 IEEE 69th Electronic Components and Technology Conference (ECTC) Pub Date : 2019-05-28 DOI: 10.1109/ECTC.2019.00098

Taejoo Hwang, D. Oh, Jaechoon Kim, Euseok Song, Taehun Kim, Kilsoo Kim, Joungphil Lee, Taehwan Kim

{"title":"The Thermal Dissipation Characteristics of The Novel System-In-Package Technology (ICE-SiP) for Mobile and 3D High-end Packages","authors":"Taejoo Hwang, D. Oh, Jaechoon Kim, Euseok Song, Taehun Kim, Kilsoo Kim, Joungphil Lee, Taehwan Kim","doi":"10.1109/ECTC.2019.00098","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00098","url":null,"abstract":"As information technologies evolve with the 4th industry revolution, such as artificial intelligence and 5G mobile communication, much more computing power and data bandwidth are required for both mobile and server systems. However, one-dimensional thermal packaging solutions such as a heat spreader or high conductive materials are not sufficient to solve the heat dissipation problems for the system-in-packages. In this research, a novel thermal dissipation technology based on two-dimensional heat flow was studied for the 5G high thermal power system-in-package modems and high performance computing logics. By applying a high thermal conductive material such as silver paste to conventional epoxy mold compound structures and creating direct high thermal dissipation paths from a bottom logic die to the heat spreader, it can bypass memory die that is more sensitive to the temperature rise than the logic die. The thermal performance of this novel technology was demonstrated using actual 5G modem system-in-packages comprised of a modem and two LPDDR4x dice. In conclusion, two-dimensional heat dissipation technique using thermal chimney is effective to reduce thermal crosstalk between top memory and bottom logic dice. Consequently, the overall system thermal performance was able to be improved by reducing heat flow through top memory dice.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"21 1","pages":"614-619"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87548914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Process Development of Power Delivery Through Wafer Vias for Silicon Interconnect Fabric 硅互连结构晶圆通孔供电工艺开发

2019 IEEE 69th Electronic Components and Technology Conference (ECTC) Pub Date : 2019-05-28 DOI: 10.1109/ECTC.2019.00093

M. Liu, Boris Vaisband, A. Hanna, Yandong Luo, Zhe Wan, S. Iyer

{"title":"Process Development of Power Delivery Through Wafer Vias for Silicon Interconnect Fabric","authors":"M. Liu, Boris Vaisband, A. Hanna, Yandong Luo, Zhe Wan, S. Iyer","doi":"10.1109/ECTC.2019.00093","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00093","url":null,"abstract":"At UCLA Center for Heterogeneous Integration and Performance Scaling (CHIPS), we have been developing a fine pitch heterogeneous wafer-scale platform with a single level of hierarchy called the silicon interconnect fabric (Si-IF). The Si-IF is a platform for heterogeneous integration of different bare dies at fine pitch (2 to 10 µm) and close proximity (<100 µm die spacing). The Si-IF platform can accommodate an entire 50 kW data center on a single 300 mm diameter wafer. Power delivery and heat extraction are fundamental challenges. To minimize the overhead of power conversion, current at mission (point-of-load) voltage is planned to be delivered directly to the assembly; this requires a uniform delivery of tens of kilo-amperes. Our approach is to deliver the current from the back of the Si-IF, using cooled Cu fins and through wafer vias (TWVs), to the front side of the wafer, where the dies are assembled facedown. TWVs are a key component of this power delivery system and are required to penetrate through the entire thickness of the Si-IF (500 - 700 µm). A process for fabrication of large-sized (100 µm diameter) TWVs for the Si-IF is described in this paper. The TWVs are etched in 500 µm Si wafer (aspect ratio of 1:5) and are designed to enable back-side power delivery to the integrated system. Each TWV exhibits a resistance of 1.1 mΩ with an extracted resistivity of 1.73⋅10^-8 Ωm. The scale and performance of these large-sized TWVs supports high current density for power delivery applications.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"8 1","pages":"579-586"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75679857","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Bladder Inflation Stretch Test Method for Reliability Characterization of Wearable Electronics 可穿戴电子产品可靠性特性的膀胱膨胀拉伸试验方法

2019 IEEE 69th Electronic Components and Technology Conference (ECTC) Pub Date : 2019-05-28 DOI: 10.1109/ECTC.2019.00065

Benjamin G. Stewart, S. Sitaraman

{"title":"Bladder Inflation Stretch Test Method for Reliability Characterization of Wearable Electronics","authors":"Benjamin G. Stewart, S. Sitaraman","doi":"10.1109/ECTC.2019.00065","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00065","url":null,"abstract":"The recent development of electronic materials that can maintain electrical performance while undergoing large applied strains have demonstrated potential for use in a new breed of electronic systems. The rapid development of these electronic systems that are flexible, stretchable, and/or wearable necessitates the concurrent development of robust mechanical and electrical test methods to improve their design and reliability. In this paper, one such mechanical test method is discussed in which a stretchable electronic test coupon is mounted onto an inflatable bladder of known geometry to induce multiaxial strains, while in-situ 4-point resistance measurement is employed to assess the device's performance and electromechanical integrity. The material combination of a stretchable screen-printed silver ink cured onto a thermoplastic polyurethane (TPU) substrate is studied given the proclivity for the use of TPU in wearable devices. A dome-shaped bladder configuration is employed in this work to study the performance of printed conductors under biaxial stretching. Various monotonic and cyclic loading regimes are employed to characterize the fatigue behavior and maximum use conditions of the samples. Volume of water displaced into the bladder during inflation is measured and correlated to the induced multiaxial strains on the mounted devices using 3D digital image correlation. Relationships between resistance and applied multiaxial strains are presented. Experimental results are compared with literature, and plausible extensions of the test method including direct printing on the bladder material are discussed.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"31 2 1","pages":"382-391"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77077626","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

A Wearable Fingernail Deformation Sensing System and Three-Dimensional Finite Element Model of Fingertip 一种可穿戴式指甲变形传感系统及指尖三维有限元模型

2019 IEEE 69th Electronic Components and Technology Conference (ECTC) Pub Date : 2019-05-28 DOI: 10.1109/ECTC.2019.00047

K. Sakuma, B. Webb, R. Narayanan, Avner Abrami, Jeff Rogers, J. Knickerbocker, S. Heisig

{"title":"A Wearable Fingernail Deformation Sensing System and Three-Dimensional Finite Element Model of Fingertip","authors":"K. Sakuma, B. Webb, R. Narayanan, Avner Abrami, Jeff Rogers, J. Knickerbocker, S. Heisig","doi":"10.1109/ECTC.2019.00047","DOIUrl":"https://doi.org/10.1109/ECTC.2019.00047","url":null,"abstract":"This paper describes the sensor, electronics, software, modeling, and characterization of a fingernail-mounted RF-connected wearable strain sensor system that measures nail deformation from finger movement. Applications to health monitoring and human computer interfaces in homes, hospitals, and workplaces are discussed. The mechanical deformation of a fingertip pressed or drawn against a plate is demonstrated using a three-dimensional finite-element linear-elastic model to predict the signal level, optimum sensor locations and the type and location of deformation expected for different finger motions. The 3D finite-element linear elastic model is derived from X-ray images of a human finger but generalized and parameterized to allow new models to be created by scaling internal and external parameters such as skin thickness and nail and finger shape to predict sensor system performance for a more general human population. Our analysis finds that a single sensor mounted in the center of the nail will respond to typical grip pressures on the fingertip with readily detectible strain amplitudes but that a multi-sensor array will be sensitive to more general haptic phenomena such as the direction and magnitude of frictional loads and loading of the distal phalangeal joint. It is shown that depending on finger use and loading the nail exhibits shifts in direction, location and sign of strain over the fingernail surface. Measurement data from a simple multi-sensor array is shown to be useful in distinguishing between load conditions, however additional sensors are required for full determination.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"23 1","pages":"270-276"},"PeriodicalIF":0.0,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80043336","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0