Process Development of Power Delivery Through Wafer Vias for Silicon Interconnect Fabric

Abstract

At UCLA Center for Heterogeneous Integration and Performance Scaling (CHIPS), we have been developing a fine pitch heterogeneous wafer-scale platform with a single level of hierarchy called the silicon interconnect fabric (Si-IF). The Si-IF is a platform for heterogeneous integration of different bare dies at fine pitch (2 to 10 µm) and close proximity (<100 µm die spacing). The Si-IF platform can accommodate an entire 50 kW data center on a single 300 mm diameter wafer. Power delivery and heat extraction are fundamental challenges. To minimize the overhead of power conversion, current at mission (point-of-load) voltage is planned to be delivered directly to the assembly; this requires a uniform delivery of tens of kilo-amperes. Our approach is to deliver the current from the back of the Si-IF, using cooled Cu fins and through wafer vias (TWVs), to the front side of the wafer, where the dies are assembled facedown. TWVs are a key component of this power delivery system and are required to penetrate through the entire thickness of the Si-IF (500 - 700 µm). A process for fabrication of large-sized (100 µm diameter) TWVs for the Si-IF is described in this paper. The TWVs are etched in 500 µm Si wafer (aspect ratio of 1:5) and are designed to enable back-side power delivery to the integrated system. Each TWV exhibits a resistance of 1.1 mΩ with an extracted resistivity of 1.73⋅10^-8 Ωm. The scale and performance of these large-sized TWVs supports high current density for power delivery applications.