C. Ko, Henry Yang, J. Lau, Ming Li, Curry Lin, Chieh-Lin Chang, Jhih-Yuan Pan, Hsing-Hui Wu, Iris Xu, Tony Chen, Zhang Li, K. Tan, Penny Lo, R. So, Y. H. Chen, N. Fan, E. Kuah, M. Lin, Y. Cheung, Eric Ng, Cao Xi, R. Beica, S. Lim, N. Lee, Mian Tao, J. Lo, Ricky S. W. Lee
{"title":"Feasibility Study of Fan-Out Panel-Level Packaging for Heterogeneous Integrations","authors":"C. Ko, Henry Yang, J. Lau, Ming Li, Curry Lin, Chieh-Lin Chang, Jhih-Yuan Pan, Hsing-Hui Wu, Iris Xu, Tony Chen, Zhang Li, K. Tan, Penny Lo, R. So, Y. H. Chen, N. Fan, E. Kuah, M. Lin, Y. Cheung, Eric Ng, Cao Xi, R. Beica, S. Lim, N. Lee, Mian Tao, J. Lo, Ricky S. W. Lee","doi":"10.1109/ECTC.2019.00010","DOIUrl":null,"url":null,"abstract":"The design, materials, process, and fabrication of a heterogeneous integration of 4 chips by a FOPLP (fan-out panel-level packaging) with chip-first and dies face-down formation are investigated in this study. Emphasis is placed on the application of a new assembly process and materials for fabricating the RDLs (redistribution layers) of the FOPLP. The panel size is 508mm x 508mm. The epoxy molding compound (EMC) is a dry-film material and is molded by lamination method. The minimum metal line width and spacing is 10µm and they are fabricated by printed circuit board (PCB) method and equipment.","PeriodicalId":6726,"journal":{"name":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","volume":"16 1","pages":"14-20"},"PeriodicalIF":0.0000,"publicationDate":"2019-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 IEEE 69th Electronic Components and Technology Conference (ECTC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ECTC.2019.00010","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
The design, materials, process, and fabrication of a heterogeneous integration of 4 chips by a FOPLP (fan-out panel-level packaging) with chip-first and dies face-down formation are investigated in this study. Emphasis is placed on the application of a new assembly process and materials for fabricating the RDLs (redistribution layers) of the FOPLP. The panel size is 508mm x 508mm. The epoxy molding compound (EMC) is a dry-film material and is molded by lamination method. The minimum metal line width and spacing is 10µm and they are fabricated by printed circuit board (PCB) method and equipment.
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