2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)最新文献_第9页

Enabling Microarchitectural Randomization in Serialized AES Implementations to Mitigate Side Channel Susceptibility 在序列化AES实现中启用微架构随机化以减轻侧信道易感性

2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2019-07-01 DOI: 10.1109/ISVLSI.2019.00064

S. Dhanuskodi, Daniel E. Holcomb

{"title":"Enabling Microarchitectural Randomization in Serialized AES Implementations to Mitigate Side Channel Susceptibility","authors":"S. Dhanuskodi, Daniel E. Holcomb","doi":"10.1109/ISVLSI.2019.00064","DOIUrl":"https://doi.org/10.1109/ISVLSI.2019.00064","url":null,"abstract":"Highly serialized implementations of the AES block cipher are used in lightweight applications where low area and low power are the primary concerns. Security of these lightweight designs becomes increasingly critical on resource-constrained devices in the Internet of Things era. The AES algorithm does not have any significant known cryptanalytic weaknesses, but keys can often be extracted by attacking implementation weaknesses using side channel information leakage or fault injection. Highly serialized AES implementations compute on individual bytes/words of data in each cycle which leaves them especially sensitive to side channel key extraction because there is less overall power consumption to obscure side channel leakages. In this work, we present an efficient AES microarchitecture that randomizes sub-round operations and reduces susceptibility to power side channel attacks. The architecture we propose is compatible with, and complementary to, all existing circuit-level side channel countermeasures. We design an 8-bit AES architecture in a commercial 16nm FinFET technology and observe an order of magnitude improvement in side channel protection at a cost of 36% more area and 25% more energy per encryption. Testchip measurement shows 0.93pJ/bit energy consumption at 10MHz.","PeriodicalId":6703,"journal":{"name":"2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"20 1","pages":"314-319"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85935098","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Hardware Implementation of Improved Fast-SSC-Flip Decoder for Polar Codes 改进的快速ssc翻转译码器的硬件实现

2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2019-07-01 DOI: 10.1109/ISVLSI.2019.00109

Jing Zeng, Yangcan Zhou, Jun Lin, Zhongfeng Wang

{"title":"Hardware Implementation of Improved Fast-SSC-Flip Decoder for Polar Codes","authors":"Jing Zeng, Yangcan Zhou, Jun Lin, Zhongfeng Wang","doi":"10.1109/ISVLSI.2019.00109","DOIUrl":"https://doi.org/10.1109/ISVLSI.2019.00109","url":null,"abstract":"Polar code has gained worldwide recognition due to its capacity-achieving property. The fast simplified successive cancellation flip (Fast-SSC-Flip) algorithm improves the frame error rate (FER) performance of successive cancellation (SC) decoders with extra metric computations. However, the metric includes exponential operations, which is inefficient to implement. In this work, one shift operation and one addition are employed to approximate the exponential operations with negligible performance loss. Besides, the metric computations of more constituent codes (Type-I to Type-V) are derived that the complexity of Fast-SSC-Flip is further reduced. Simulation results show that the FER performance of the improved Fast-SSC-Flip algorithm with list size λ = 8 outperforms that of the Fast-SSC algorithm by 0.7dB. Moreover, based on the proposed algorithm, an efficient hardware architecture is first developed. It uses less look up tables and achieves a maximum throughput of 140.6 Mbps at high SNR on the Altera Stratix IV EP4SGX530KH40C2 FPGA. Compared with the state of art Fast-SSC implementation, the proposed architecture has a higher resource utilization efficiency (throughput per look-up tables). Under the 28 nm CMOS technology, the throughput can reach up to 483.8 Mbps at a clock frequency of 704 MHz.","PeriodicalId":6703,"journal":{"name":"2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"88 1","pages":"580-585"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85633660","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Machine Learning-Based Processor Adaptability Targeting Energy, Performance, and Reliability 基于机器学习的处理器适应性:能量、性能和可靠性

2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2019-07-01 DOI: 10.1109/ISVLSI.2019.00037

A. L. Sartor, P. H. E. Becker, Stephan Wong, R. Marculescu, A. C. S. Beck

引用次数: 1

ASSET: Architectures for Smart Security of Non-Volatile Memories 资产:非易失性存储器的智能安全架构

2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2019-07-01 DOI: 10.1109/ISVLSI.2019.00070

S. Swami, K. Mohanram

{"title":"ASSET: Architectures for Smart Security of Non-Volatile Memories","authors":"S. Swami, K. Mohanram","doi":"10.1109/ISVLSI.2019.00070","DOIUrl":"https://doi.org/10.1109/ISVLSI.2019.00070","url":null,"abstract":"Computing systems that integrate advanced non-volatile memories (NVMs) are vulnerable to several security attacks that threaten (i) data confidentiality, (ii) data availability, and (iii) data integrity. This paper proposes Architectures for Smart Security of NVMs (AS-SET), which integrates five low overhead, high performance security solutions—SECRET [1], COVERT [2], ACME [3], ARSE-NAL [4], and STASH [5]—to thwart these attacks on NVM systems. SECRET is a low cost security solution that employs counter mode encryption (CME) for data confidentiality in multi-/triple-level cell (i.e., MLC/TLC) NVMs. COVERT and ACME complement SECRET to improve system availability of CME. ARSENAL integrates CME and Bonsai Merkle Tree (BMT) authentication to thwart data confidentiality and integrity attacks, respectively, in NVMs and simultaneously enables instant data recovery (IDR) on power/system failures. Finally, STASH is the first comprehensive end-to-end security architecture for state-of-the-art smart hybrid memories (SHMs). STASH integrates (i) CME for data confidentiality, (ii) page-level MT authentication for data integrity, (iii) recovery-compatible MT updates to withstand power or system failures, and (iv) page-migration friendly security meta-data management. This paper thus addresses the core security challenges of next-generation NVM systems.","PeriodicalId":6703,"journal":{"name":"2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"182 1","pages":"348-353"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77589898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Self Timed SRAM Array with Enhanced low Voltage Read and Write Capability 具有增强低电压读写能力的自定时SRAM阵列

2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2019-07-01 DOI: 10.1109/ISVLSI.2019.00117

Prasad Vernekar, Nithin Kumar Yernad Balachandra, V. M. Harishchandra

引用次数: 1

Minimization of Flare in EUVL by Simultaneous Wire Segment Perturbation and Dummification 同时线段摄动和伪化的EUVL中耀斑最小化

2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2019-07-01 DOI: 10.1109/ISVLSI.2019.00047

S. Paul, Pritha Banerjee, S. Sur-Kolay

引用次数: 1

A Multi-phase Time-to-Digital Converter Differential Vernier Ring Oscillato 多相时间-数字转换器差分游标环振荡器

2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2019-07-01 DOI: 10.1109/ISVLSI.2019.00069

A. Annagrebah, E. Bechetoille, I. Laktineh, H. Chanal, P. Russo, H. Mathez

{"title":"A Multi-phase Time-to-Digital Converter Differential Vernier Ring Oscillato","authors":"A. Annagrebah, E. Bechetoille, I. Laktineh, H. Chanal, P. Russo, H. Mathez","doi":"10.1109/ISVLSI.2019.00069","DOIUrl":"https://doi.org/10.1109/ISVLSI.2019.00069","url":null,"abstract":"is paper reports the development of an adjustable, Time-to-Digital Converter (TDC) based on two vernier Ring Oscillators (RO). The TDC aims to measure timing in Resistive Plate Chamber (RPC) detector for CMS experiment. Considering previous designs, the contribution from power supply noise and intrinsic transistor noise had been minimizing with differential stages and proper transistor sizing. In order to reduce the dead time inherent to Vernier TDC architecture, as many Phase Detector (PD) as possible had been implemented. Such functionality permits to choose whether reducing the dead time or measuring redundantly the start-stop time difference for an improved resolution. The 81-PD Matrix is the originality of the design. Indeed, the information of the start-stop time is present at each inverter output with a predictable offset in term of time. The inverter architecture introduces a constant delay at each stage of the chain with phase inversion. By recording the counter when a phase detection occurs at each inverter output permitted to revert back to the start-stop time. The prototype TDC fabricated in a 130-nm technology consumes 8.5 mW power under 1.2-V supply. The measurement of this chip shown a timing accuracy of 5.48 ps at a timing resolution of 8 ps for the first data allowed by the first phase detection","PeriodicalId":6703,"journal":{"name":"2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"22 1","pages":"344-347"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85404019","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

MRAM-Based Stochastic Oscillators for Adaptive Non-Uniform Sampling of Sparse Signals in IoT Applications 物联网应用中基于mram的稀疏信号自适应非均匀采样随机振荡器

2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2019-07-01 DOI: 10.1109/ISVLSI.2019.00079

Soheil Salehi, Alireza Zaeemzadeh, Adrian Tatulian, N. Rahnavard, R. Demara

{"title":"MRAM-Based Stochastic Oscillators for Adaptive Non-Uniform Sampling of Sparse Signals in IoT Applications","authors":"Soheil Salehi, Alireza Zaeemzadeh, Adrian Tatulian, N. Rahnavard, R. Demara","doi":"10.1109/ISVLSI.2019.00079","DOIUrl":"https://doi.org/10.1109/ISVLSI.2019.00079","url":null,"abstract":"Recent advances to hardware integration and realization of highly-efficient Compressive Sensing (CS) approaches have inspired novel circuit and architectural-level approaches. These embrace the challenge to design more optimal nonuniform CS solutions that consider device-level constraints for IoT applications wherein lifetime energy, device area, and manufacturing costs are highly-constrained, but meanwhile, the sensing environment is rapidly changing. In this manuscript, we develop a novel adaptive hardware-based approach for non-uniform compressive sampling of sparse and time-varying signals. The proposed Adaptive Sampling of Sparse IoT signals via STochastic-oscillators (ASSIST) approach intelligently generates the CS measurement matrix by distributing the sensing energy among coefficients by considering the signal characteristics such as sparsity rate and noise level obtained in the previous time step. In our proposed approach, Magnetic Random Access Memory (MRAM)-based stochastic oscillators are utilized to generate the random bitstreams used in the CS measurement matrix. SPICE and MATLAB circuit-algorithm simulation results indicate that ASSIST efficiently achieves the desired non-uniform recovery of the original signals with varying sparsity rates and noise levels.","PeriodicalId":6703,"journal":{"name":"2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"28 1","pages":"403-408"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89941504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

Distributed Pulse Rotary Traveling Wave VCO: Architecture and Design 分布式脉冲旋转行波压控振荡器:结构与设计

2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2019-07-01 DOI: 10.1109/ISVLSI.2019.00051

Prashansa Mukim, Aditya Dalakoti, D. McCarthy, Brandon Pon, Carrie Segal, Merritt Miller, J. Buckwalter, F. Brewer

引用次数: 0

A Framework for the Analysis of Throughput-Constraints of SNNs on Neuromorphic Hardware 神经形态硬件上snn吞吐量约束分析框架

2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2019-07-01 DOI: 10.1109/ISVLSI.2019.00043

Adarsha Balaji, Anup Das

{"title":"A Framework for the Analysis of Throughput-Constraints of SNNs on Neuromorphic Hardware","authors":"Adarsha Balaji, Anup Das","doi":"10.1109/ISVLSI.2019.00043","DOIUrl":"https://doi.org/10.1109/ISVLSI.2019.00043","url":null,"abstract":"Spiking neural networks (SNN) are efficient computation models to infer spacio-temporal pattern recognition applications on neuromorphic hardware. Neuromorphic hardware are typically designed using interconnected crossbars, with each crossbar containing a structure of fully connected neurons. In order to ensure application performance such as accuracy and system performance such as throughput and resource utilization, SNNs need to be efficiently mapped on neuromorphic hardware. To address this, we propose a design flow to partition and map SNN-based applications on neuromorphic hardware, with an aim to enhance application and system performance. The design flow operates in two steps : (1) a two-step clustering technique to partition trained SNNs into clusters of neurons and synapses, with an aim to minimize inter-cluster spike communication, (2) mapping and scheduling the clusters on to crossbars-based architectures, modeled using Synchronous Data-flow Graphs (SDFGs). The SDFG model incorporates hardware constraints such as I/O bandwidth of crossbars and synaptic memory while analyzing the throughput of the modeled system. Our design-flow integrates CARLsim, a GPU-accelerated application-level SNN simulator with SDF3, a tool to map SDFG on hardware. We evaluate the design-flow using synthetic and realistic SNN-based applications. We show that, for throughput constrained applications, we achieve a 21.74% and 15.03% reduction in memory usage and utilization of the time-multiplexed interconnect, compared to a state of the art approach.","PeriodicalId":6703,"journal":{"name":"2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"1 1","pages":"193-196"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75049569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 22