Self Timed SRAM Array with Enhanced low Voltage Read and Write Capability

Abstract

The scaling of technology resulted in shrinking of device sizes, however suffers from threshold variation. These variations impact the performance and stability of static random access memory (SRAM). The proposed work takes the advantage of the conventional Replica-Bit-Line (RBL) technique to design a self-timed SRAM control circuit which keeps track of timing variations and generated control signals. A variable wordline scheme is proposed to ensure successful read and write operation of SRAM at low voltages. The 2 Kb (2048 bits) SRAM designed in 65 nm UMC technology, operates with clock frequency reaching upto 1 GHz at the nominal supply voltage of 1.2 V and at 50 MHz with the supply voltage of 0.58 V. The variations in the Sense Amplifier Enable (SAE) generation are reduced upto 92% compared to the conventional RBL technique.