2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)最新文献

Improving Logic Optimization in Sequential Circuits using Majority-inverter Graphs 利用多数逆变器图改进顺序电路的逻辑优化

2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2019-07-15 DOI: 10.1109/ISVLSI.2019.00049

Walter Lau Neto, Xifan Tang, Max Austin, L. Amarù, P. Gaillardon

{"title":"Improving Logic Optimization in Sequential Circuits using Majority-inverter Graphs","authors":"Walter Lau Neto, Xifan Tang, Max Austin, L. Amarù, P. Gaillardon","doi":"10.1109/ISVLSI.2019.00049","DOIUrl":"https://doi.org/10.1109/ISVLSI.2019.00049","url":null,"abstract":"Majority-inverter graph (MIG) is a recently introduced Boolean network that enables efficient logic manipulation. Recent works show that MIGs are capable of achieving significant improvements in area, delay, and power when comparing to current academic and commercial tools. However, current MIG optimizations are limited to combinational circuits, missing the sequential elements which are ubiquitous in practical implementations. This paper is the first to study the sequential optimization opportunities using MIGs. The presented extension leverages the efficiency of MIGs area and depth-oriented rewriting algorithms for combinational circuits in sequential networks. Experimental results showed that, averaged over the OpenCores benchmark suite, (1) when considering technology-independent evaluations, compared to a popular academic tool, our MIG-based sequential optimization brings an improvement of 9% and 38% in area and delay respectively; (2) when using a standard optimization+technology mapping flow for ASICs with a 7nm predictive standard cell library, the proposed sequential optimizer outperforms both academic and commercial tools in energy-delay product (EDP) by 12% and 4% respectively and area-delay product (ADP) by 13% and 7% respectively.","PeriodicalId":6703,"journal":{"name":"2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"28 1","pages":"224-229"},"PeriodicalIF":0.0,"publicationDate":"2019-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77656693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Dark-Silicon Inspired Energy Efficient Hierarchical TDM NoC 暗硅启发的节能分层TDM NoC

2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2019-07-15 DOI: 10.1109/ISVLSI.2019.00030

Salma Hesham, D. Göhringer, M. A. E. Ghany

{"title":"Dark-Silicon Inspired Energy Efficient Hierarchical TDM NoC","authors":"Salma Hesham, D. Göhringer, M. A. E. Ghany","doi":"10.1109/ISVLSI.2019.00030","DOIUrl":"https://doi.org/10.1109/ISVLSI.2019.00030","url":null,"abstract":"In this paper, we propose a dark-silicon inspired hierarchical Time-Division-Multiplexing (TDM) network-on-chip (NoC) with online distributed setup-scheme for slots allocation. In addition to the normal mesh routers, we propose hierarchical routers, making use of the dim silicon parts of the chip, to hierarchically connect quad-routers units. Normal routers operate at full-chip-frequency at supply of 1. 2V, while hierarchical routers operate at half-chip-frequency and supply of 0.8V with double datawidth and half slot-size. Routers follow a proposed architecture that distinguishes between data-path and control-setup sub-routers. This allows separate clocking and operating supplies between data and control and to keep the control as a single-slot-cycle design independent of the data slot size. The proposed NoC architecture as well as a base NoC architecture from state-of-the-art are evaluated under uniform random traffic using Synopsys VCS and synthesized using Synopsys Design Compiler for SAED90nm technology. With the same power budget of the base NoC, the proposed architecture provides up to 74% improved setup latency, 32% increased NoC saturation load, and 21% higher success rates. The proposed hierarchical quad is based on leveraging the dim silicon parts of the chip for an energy efficient design. Though it consumes 1.78 times the area of the base quad, however with 56% under-clocked area operating at half the maximum chip frequency; thus reducing the power density to 52% of the base NoC.","PeriodicalId":6703,"journal":{"name":"2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"87 1","pages":"116-121"},"PeriodicalIF":0.0,"publicationDate":"2019-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78266186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Linear Optimization for Memristive Device in Neuromorphic Hardware 神经形态硬件中记忆器件的线性优化

2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2019-07-15 DOI: 10.1109/ISVLSI.2019.00088

Jingyan Fu, Zhiheng Liao, Na Gong, Jinhui Wang

引用次数: 4

TrustFlow: A Trusted Memory Support for Data Flow Integrity TrustFlow:支持数据流完整性的可信内存

2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2019-07-15 DOI: 10.1109/ISVLSI.2019.00063

C. Bresch, D. Hély, Stéphanie Chollet, I. Parissis

引用次数: 2

Modeling Hardware Trojans in 3D ICs 3D集成电路中的硬件木马建模

2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2019-07-15 DOI: 10.1109/ISVLSI.2019.00093

Zhiming Zhang, Qiaoyan Yu

引用次数: 5

Morphed Standard Cell Layouts for Pin Length Reduction 变形的标准单元布局引脚长度减少

2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2019-07-15 DOI: 10.1109/ISVLSI.2019.00025

Cheng-Wei Tai, Rung-Bin Lin

引用次数: 4

CAESAR-MPSoC: Dynamic and Efficient MPSoC Security Zones CAESAR-MPSoC:动态和高效的MPSoC安全区域

2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2019-07-15 DOI: 10.1109/ISVLSI.2019.00092

Siavoosh Payandeh Azad, G. Jervan, Michael Tempelmeier, Martha Johanna Sepúlveda

{"title":"CAESAR-MPSoC: Dynamic and Efficient MPSoC Security Zones","authors":"Siavoosh Payandeh Azad, G. Jervan, Michael Tempelmeier, Martha Johanna Sepúlveda","doi":"10.1109/ISVLSI.2019.00092","DOIUrl":"https://doi.org/10.1109/ISVLSI.2019.00092","url":null,"abstract":"Dynamic security zones in Multiprocessor System-on-Chip (MP-SoC) has been used to isolate sensitive applications from possible attackers. These physical wrappers are usually configured through programmable hardware firewalls. Previous works have shown the efficiency of this security mechanism against a wide variety of attacks. However, the security zone configuration is performed in an unprotected way, exposing the system to attacks caused by rogue firewall update. In this work we propose CAESAR-MPSoC, an enhanced MPSoC able to ensure the protected configuration of the firewalls through encrypted and authenticated reconfiguration packets. To this end, we present two contributions. First, we integrate two CAESAR (Competition for Authenticated Encryption: Security, Applicability, and Robustness) hardware IP cores, ASCON and AEGIS, into MPSoCs. Second, we developed a light-weight interface that allows to plug-in the different CAESAR cores into MPSoC environment. Third, we show the protected configuration of security zones. Fourth, we evaluate the security, area and cost of CAESAR-MPSoC. The results show that our solution is feasible and effective to allow the protected and efficient security zone configuration.","PeriodicalId":6703,"journal":{"name":"2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"27 1","pages":"477-482"},"PeriodicalIF":0.0,"publicationDate":"2019-07-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79016018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

Optimization of Comparator Selection Algorithm for TIQ Flash ADC Using Dynamic Programming Approach TIQ Flash ADC比较器选择算法的动态规划优化

2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2019-07-15 DOI: 10.1109/ISVLSI.2019.00095

Ali Ozdemir, Mshabab Alrizah, Kyusun Choi

引用次数: 4

PageCmp: Bandwidth Efficient Page Deduplication through In-memory Page Comparison PageCmp:通过内存中页面比较的带宽高效页面重复数据删除

2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2019-07-15 DOI: 10.1109/ISVLSI.2019.00023

Mehrnoosh Raoufi, Quan Deng, Youtao Zhang, Jun Yang

引用次数: 4

Design of a Safe Convolutional Neural Network Accelerator 一种安全卷积神经网络加速器的设计

2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2019-07-15 DOI: 10.1109/ISVLSI.2019.00053

Zheng Xu, J. Abraham

引用次数: 1