2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)最新文献_第8页

Exploiting Near-Memory Processing Architectures for Bayesian Neural Networks Acceleration 利用近内存处理架构加速贝叶斯神经网络

2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2019-07-01 DOI: 10.1109/ISVLSI.2019.00045

Yinglin Zhao, Jianlei Yang, Xiaotao Jia, Xueyan Wang, Zhaohao Wang, W. Kang, Youguang Zhang, Weisheng Zhao

引用次数: 0

A One-Cycle FIFO Buffer for Memory Management Units in Manycore Systems 多核系统中内存管理单元的单周期FIFO缓冲器

2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2019-07-01 DOI: 10.1109/ISVLSI.2019.00056

A. Gordon-Ross, S. Abdel-Hafeez, Mohamad Hammam Alsafrjalani

引用次数: 6

Using Harmonized Parabolic Synthesis to Implement a Single-Precision Floating-Point Square Root Unit 用协调抛物综合实现单精度浮点平方根单位

2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2019-07-01 DOI: 10.1109/ISVLSI.2019.00116

Süleyman Savas, Y. Atwa, T. Nordström, Z. Ul-Abdin

{"title":"Using Harmonized Parabolic Synthesis to Implement a Single-Precision Floating-Point Square Root Unit","authors":"Süleyman Savas, Y. Atwa, T. Nordström, Z. Ul-Abdin","doi":"10.1109/ISVLSI.2019.00116","DOIUrl":"https://doi.org/10.1109/ISVLSI.2019.00116","url":null,"abstract":"This paper proposes a novel method for performing square root operation on floating-point numbers represented in IEEE-754 single-precision (binary32) format. The method is implemented using Harmonized Parabolic Synthesis. It is implemented with and without pipeline stages individually and synthesized for two different Xilinx FPGA boards. The implementations show better resource usage and latency results when compared to other similar works including Xilinx intellectual property (IP) that uses the CORDIC method. Any method calculating the square root will make approximation errors. Unless these errors are distributed evenly around zero, they can accumulate and give a biased result. An attractive feature of the proposed method is the fact that it distributes the errors evenly around zero, in contrast to CORDIC for instance. Due to the small size, low latency, high throughput, and good error properties, the presented floating-point square root unit is suitable for high performance embedded systems. It can be integrated into a processor's floating point unit or be used as a stand-alone accelerator.","PeriodicalId":6703,"journal":{"name":"2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"64 1","pages":"621-626"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74504121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

An Asynchronous Analog to Digital Converter for Video Camera Applications 用于视频摄像机的异步模数转换器

2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2019-07-01 DOI: 10.1109/ISVLSI.2019.00040

R. Sunil, K. SiddharthR., Nithin Y. B. Kumar, M. H. Vasantha

引用次数: 1

Logic Synthesis for Hybrid CMOS-ReRAM Sequential Circuits 混合CMOS-ReRAM顺序电路的逻辑综合

2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2019-07-01 DOI: 10.1109/ISVLSI.2019.00084

Saman Froehlich, S. Shirinzadeh, R. Drechsler

引用次数: 1

Securing a Wireless Network-on-Chip Against Jamming Based Denial-of-Service Attacks 保护无线片上网络免受基于干扰的拒绝服务攻击

2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2019-07-01 DOI: 10.1109/ISVLSI.2019.00065

Abhishek Vashist, Andrew Keats, Sai Manoj Pudukotai Dinakarrao, A. Ganguly

{"title":"Securing a Wireless Network-on-Chip Against Jamming Based Denial-of-Service Attacks","authors":"Abhishek Vashist, Andrew Keats, Sai Manoj Pudukotai Dinakarrao, A. Ganguly","doi":"10.1109/ISVLSI.2019.00065","DOIUrl":"https://doi.org/10.1109/ISVLSI.2019.00065","url":null,"abstract":"Wireless Networks-on-Chips (NoCs) have emerged as a panacea to the non-scalable multi-hop data transmission paths in traditional wired NoC architectures. Using low-power transceivers in NoC switches, novel Wireless NoC (WiNoC) architectures have been shown to achieve higher energy efficiency with improved peak bandwidth and reduced on-chip data transfer latency. However, using wireless interconnects for data transfer within a chip makes the on-chip communications vulnerable to various security threats from either external attackers or internal hardware Trojans (HTs). In this work, we propose a mechanism to make the wireless communication in a WiNoC secure against persistent jamming based Denial-of-Service attacks from both external and internal attackers. Persistent jamming attacks on the on-chip wireless medium will cause interference in data transfer over the duration of the attack resulting in errors in contiguous bits, known as burst errors. Therefore, we use a burst error correction code to monitor the rate of burst errors received over the wireless medium and deploy a Machine Learning (ML) classifier to detect the persistent jamming attack and distinguish it from random burst errors. In the event of jamming attack, alternate routing strategies are proposed to avoid the DoS attack over the wireless medium, so that a secure data transfer can be sustained even in the presence of jamming. We evaluate the proposed technique on a secure WiNoC in the presence of DoS attacks. It has been observed that with the proposed defense mechanisms, WiNoC can outperform a wired NoC even in presence of attacks in terms of performance and security. On an average, 99.87% attack detection was achieved with the chosen ML Classifiers. A bandwidth degradation of <3% is experienced in the event of internal attack, while the wireless interconnects are disabled in the presence of an external attacker.","PeriodicalId":6703,"journal":{"name":"2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"33 1","pages":"320-325"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80432429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Energy-Efficient Embedded Inference of SVMs on FPGA 基于FPGA的支持向量机节能嵌入式推理

2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2019-07-01 DOI: 10.1109/ISVLSI.2019.00038

O. Elgawi, A. Mutawa, Afaq Ahmad

引用次数: 6

A Novel Single/Double Precision Normalized IEEE 754 Floating-Point Adder/Subtracter 一种新的单/双精度归一化IEEE 754浮点加/减器

2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2019-07-01 DOI: 10.1109/ISVLSI.2019.00058

Brett Mathis, J. Stine

引用次数: 4

When Neural Architecture Search Meets Hardware Implementation: from Hardware Awareness to Co-Design 当神经架构搜索遇到硬件实现:从硬件感知到协同设计

2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2019-07-01 DOI: 10.1109/ISVLSI.2019.00014

Xinyi Zhang, Weiwen Jiang, Yiyu Shi, J. Hu

{"title":"When Neural Architecture Search Meets Hardware Implementation: from Hardware Awareness to Co-Design","authors":"Xinyi Zhang, Weiwen Jiang, Yiyu Shi, J. Hu","doi":"10.1109/ISVLSI.2019.00014","DOIUrl":"https://doi.org/10.1109/ISVLSI.2019.00014","url":null,"abstract":"Neural Architecture Search (NAS), that automatically identifies the best network architecture, is a promising technique to respond to the ever-growing demand for application-specific Artificial Intelligence (AI). On the other hand, a large number of research efforts have been put on implementing and optimizing AI applications on the hardware. Out of all leading computation platforms, Field Programmable Gate Arrays (FPGAs) stand out due to its flexibility and versatility over ASICs and its efficiency over CPUs and GPUs. To identify the best neural architecture and hardware implementation pair, a number of research works are emerging to involve the awareness of hardware efficiency in the NAS process, which is called \"hardware-aware NAS\". Unlike the conventional NAS with a mono-criteria of accuracy, hardware-aware NAS is a multi-objective optimization problem, which aims to identify the best network and hardware pair to maximize accuracy with guaranteed hardware efficiency. Most recently, the co-design of neural architecture and hardware has been put forward to further push forward the Pareto frontier between accuracy and efficiency trade-off. This paper will review and discuss the current progress in the neural architecture search and the implementation on hardware.","PeriodicalId":6703,"journal":{"name":"2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"20 1","pages":"25-30"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89423416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 24

ASSET: Architectures for Smart Security of Non-Volatile Memories 资产:非易失性存储器的智能安全架构

2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) Pub Date : 2019-07-01 DOI: 10.1109/ISVLSI.2019.00070

S. Swami, K. Mohanram

{"title":"ASSET: Architectures for Smart Security of Non-Volatile Memories","authors":"S. Swami, K. Mohanram","doi":"10.1109/ISVLSI.2019.00070","DOIUrl":"https://doi.org/10.1109/ISVLSI.2019.00070","url":null,"abstract":"Computing systems that integrate advanced non-volatile memories (NVMs) are vulnerable to several security attacks that threaten (i) data confidentiality, (ii) data availability, and (iii) data integrity. This paper proposes Architectures for Smart Security of NVMs (AS-SET), which integrates five low overhead, high performance security solutions—SECRET [1], COVERT [2], ACME [3], ARSE-NAL [4], and STASH [5]—to thwart these attacks on NVM systems. SECRET is a low cost security solution that employs counter mode encryption (CME) for data confidentiality in multi-/triple-level cell (i.e., MLC/TLC) NVMs. COVERT and ACME complement SECRET to improve system availability of CME. ARSENAL integrates CME and Bonsai Merkle Tree (BMT) authentication to thwart data confidentiality and integrity attacks, respectively, in NVMs and simultaneously enables instant data recovery (IDR) on power/system failures. Finally, STASH is the first comprehensive end-to-end security architecture for state-of-the-art smart hybrid memories (SHMs). STASH integrates (i) CME for data confidentiality, (ii) page-level MT authentication for data integrity, (iii) recovery-compatible MT updates to withstand power or system failures, and (iv) page-migration friendly security meta-data management. This paper thus addresses the core security challenges of next-generation NVM systems.","PeriodicalId":6703,"journal":{"name":"2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)","volume":"182 1","pages":"348-353"},"PeriodicalIF":0.0,"publicationDate":"2019-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77589898","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0