2010 IEEE International Solid-State Circuits Conference - (ISSCC)最新文献_第3页

Session 6 overview: displays & biomedical devices 第6部分概述:显示器和生物医学设备

2010 IEEE International Solid-State Circuits Conference - (ISSCC) Pub Date : 2010-03-18 DOI: 10.1109/ISSCC.2010.5434079

Iliana Fujimori-Chen, R. Thewes

引用次数: 0

Suppression of flicker noise upconversion in a 65nm CMOS VCO in the 3.0-to-3.6GHz band 3.0 ~ 3.6 ghz频段65nm CMOS VCO闪烁噪声上变频抑制

2010 IEEE International Solid-State Circuits Conference - (ISSCC) Pub Date : 2010-03-18 DOI: 10.1109/ISSCC.2010.5434054

S. Levantino, Marco Zanuso, C. Samori, A. Lacaita

引用次数: 43

A configurable SRAM with constant-negative-level write buffer for low-voltage operation with 0.149µm2 cell in 32nm high-k metal-gate CMOS 采用32nm高k金属栅极CMOS，采用0.149µm2电池，设计了一种具有恒定负电平写入缓冲器的可配置SRAM，用于低压操作

2010 IEEE International Solid-State Circuits Conference - (ISSCC) Pub Date : 2010-03-18 DOI: 10.1109/ISSCC.2010.5433813

Y. Fujimura, O. Hirabayashi, T. Sasaki, A. Suzuki, A. Kawasumi, Y. Takeyama, K. Kushida, G. Fukano, A. Katayama, Y. Niki, T. Yabe

引用次数: 34

3.3GHz DCO with a frequency resolution of 150Hz for All-digital PLL 3.3GHz DCO，频率分辨率为150Hz，用于全数字锁相环

2010 IEEE International Solid-State Circuits Conference - (ISSCC) Pub Date : 2010-03-18 DOI: 10.1109/ISSCC.2010.5434057

Luca Fanori, A. Liscidini, Rinaldo Castello

{"title":"3.3GHz DCO with a frequency resolution of 150Hz for All-digital PLL","authors":"Luca Fanori, A. Liscidini, Rinaldo Castello","doi":"10.1109/ISSCC.2010.5434057","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5434057","url":null,"abstract":"In all-digital phase-locked loops (ADPLLs), the quantization noise introduced by the frequency discretization in the digitally controlled oscillator (DCO) can affect the performance in terms of out-of-band phase noise. In particular, the additional quantization noise has to be kept significantly lower than the intrinsic oscillator phase-noise, mandating a very fine frequency resolution (e.g. less than one kHz in GSM) [1]. Typically, in LC oscillators, the digital tuning is realized using two (or more) capacitor banks for coarse and fine tuning. The first bank is used to compensate process and temperature variation and to select the channel while the second is required for the DCO modulation inside the PLL. Since the coarse tuning range can be several hundred MHz (e.g. 800MHz in GSM [1]), a frequency resolution in the range of kHz can result in unitary elements for the capacitor banks of the order of atto-Farads. Although such values can be achieved by means of capacitive divider networks [2], the sensitivity to mismatches and parasitics of these solutions limit the robustness of the design. Staszewski et al. solved this problem by introducing a dithering of the 3 less significant bits of the DCO frequency control word [1]. This approach reduces considerably the equivalent DCO frequency resolution (from 12kHz to 30Hz) but, as occurs in any ΔΣ data converter, the quantization noise is moved to higher frequencies where generally the phase-noise specifications are more challenging. Due to this problem, the frequency of dithering must be significantly increased (225MHz) to satisfy the emission mask requirements far away from the carrier [1].","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"28 1","pages":"48-49"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85312306","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

A fully integrated 802.15.4a IR-UWB Transceiver in 0.13µm CMOS with digital RRC synthesis 全集成802.15.4a IR-UWB收发器，0.13µm CMOS，数字RRC合成

2010 IEEE International Solid-State Circuits Conference - (ISSCC) Pub Date : 2010-03-18 DOI: 10.1109/ISSCC.2010.5433957

Sanghoon Joo, Wu-Hsin Chen, Tae-Young Choi, M. Oh, Joo-Ho Park, Jae-Young Kim, B. Jung

引用次数: 42

A 12b 22.5/45MS/s 3.0mW 0.059mm2 CMOS SAR ADC achieving over 90dB SFDR 12b 22.5/45MS/s 3.0mW 0.059mm2 CMOS SAR ADC, SFDR超过90dB

2010 IEEE International Solid-State Circuits Conference - (ISSCC) Pub Date : 2010-03-18 DOI: 10.1109/ISSCC.2010.5433830

Wenbo Liu, P. Huang, Y. Chiu

引用次数: 142

A wafer-level heterogeneous technology integration for flexible pseudo-SoC 柔性伪soc的晶圆级异构技术集成

2010 IEEE International Solid-State Circuits Conference - (ISSCC) Pub Date : 2010-03-18 DOI: 10.1109/ISSCC.2010.5434011

H. Yamada, Yutaka Onozuka, A. Iida, K. Itaya, H. Funaki

引用次数: 6

A two-phase switching hybrid supply modulator for polar transmitters with 9% efficiency improvement 一种用于极性发射机的两相开关混合电源调制器，效率提高9%

2010 IEEE International Solid-State Circuits Conference - (ISSCC) Pub Date : 2010-03-18 DOI: 10.1109/ISSCC.2010.5433989

Ying Wu, P. Mok

{"title":"A two-phase switching hybrid supply modulator for polar transmitters with 9% efficiency improvement","authors":"Ying Wu, P. Mok","doi":"10.1109/ISSCC.2010.5433989","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5433989","url":null,"abstract":"Emerging polar transmitters for highly efficient and linear power amplifiers (PAs) demand for high-efficiency, high-bandwidth and low-ripple supply modulators. In [1], a linear regulator is used; however, its efficiency is low at low power levels. A switched-mode power supply (SMPS) is used in [2]; but the high switching loss due to high switching frequency (necessary for high bandwidth) limits the maximum efficiency to ∼76%. A hybrid amplifier (HA) topology combining both linear amplifier (LA) and switching amplifier (SA) is used in some recent work [3, 4]. In this topology, a high-bandwidth LA replicates the input envelope voltage Vin at its output Vo; while the high-efficiency SA supplies most of the load current within its bandwidth. Yet, the tracking bandwidth is finite in [3]; and the LA in [4] needs to supply most of the high-frequency load current due to the exceptionally large inductor (20µH) used for realizing small output ripple; and therefore, limiting the dynamic efficiency. Figure 10.1.1 shows the proposed wideband HA featuring two-phase switching (2PHSW) for reducing ripple and improving static efficiency, and a feedforward bandpass filter (FF-BBF) for enhancing dynamic efficiency.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"263 1","pages":"196-197"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75107036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

A 900MHz direct ΔΣ receiver in 65nm CMOS 900MHz直接ΔΣ接收器在65nm CMOS

2010 IEEE International Solid-State Circuits Conference - (ISSCC) Pub Date : 2010-03-18 DOI: 10.1109/ISSCC.2010.5434049

K. Koli, J. Jussila, P. Sivonen, Sami Kallioinen, A. Pärssinen

引用次数: 12

A 4.5mW/Gb/s 6.4Gb/s 22+1-lane source-synchronous link rx core with optional cleanup PLL in 65nm CMOS 一个4.5mW/Gb/s 6.4Gb/s 22+1通道源同步链路rx核心，带有可选的65纳米CMOS清理锁相环

2010 IEEE International Solid-State Circuits Conference - (ISSCC) Pub Date : 2010-03-18 DOI: 10.1109/ISSCC.2010.5434008

引用次数: 8