A 4.5mW/Gb/s 6.4Gb/s 22+1-lane source-synchronous link rx core with optional cleanup PLL in 65nm CMOS

Abstract

Source synchronous links are often used in server systems for multi-lane high-speed serial applications such as connecting CPU to CPU, to memory, or to bridge chips due to their inherent tracking of correlated jitter [1]. This paper presents a low-power compact differential source synchronous receiver PHY comprised of 22 data lanes and 1 clock lane. This receiver, plus a corresponding transmitter and impedance calibration macro, support multiple differential and ground terminated link standards at 4.8 to 6.4Gb/s, such as Intel QPI 1.0 and IBM proprietary memory links.