{"title":"一个4.5mW/Gb/s 6.4Gb/s 22+1通道源同步链路rx核心，带有可选的65纳米CMOS清理锁相环","authors":"","doi":"10.1109/ISSCC.2010.5434008","DOIUrl":null,"url":null,"abstract":"Source synchronous links are often used in server systems for multi-lane high-speed serial applications such as connecting CPU to CPU, to memory, or to bridge chips due to their inherent tracking of correlated jitter [1]. This paper presents a low-power compact differential source synchronous receiver PHY comprised of 22 data lanes and 1 clock lane. This receiver, plus a corresponding transmitter and impedance calibration macro, support multiple differential and ground terminated link standards at 4.8 to 6.4Gb/s, such as Intel QPI 1.0 and IBM proprietary memory links.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"67 1","pages":"160-161"},"PeriodicalIF":0.0000,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"A 4.5mW/Gb/s 6.4Gb/s 22+1-lane source-synchronous link rx core with optional cleanup PLL in 65nm CMOS\",\"authors\":\"\",\"doi\":\"10.1109/ISSCC.2010.5434008\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Source synchronous links are often used in server systems for multi-lane high-speed serial applications such as connecting CPU to CPU, to memory, or to bridge chips due to their inherent tracking of correlated jitter [1]. This paper presents a low-power compact differential source synchronous receiver PHY comprised of 22 data lanes and 1 clock lane. This receiver, plus a corresponding transmitter and impedance calibration macro, support multiple differential and ground terminated link standards at 4.8 to 6.4Gb/s, such as Intel QPI 1.0 and IBM proprietary memory links.\",\"PeriodicalId\":6418,\"journal\":{\"name\":\"2010 IEEE International Solid-State Circuits Conference - (ISSCC)\",\"volume\":\"67 1\",\"pages\":\"160-161\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-03-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 IEEE International Solid-State Circuits Conference - (ISSCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.2010.5434008\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2010.5434008","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 4.5mW/Gb/s 6.4Gb/s 22+1-lane source-synchronous link rx core with optional cleanup PLL in 65nm CMOS
Source synchronous links are often used in server systems for multi-lane high-speed serial applications such as connecting CPU to CPU, to memory, or to bridge chips due to their inherent tracking of correlated jitter [1]. This paper presents a low-power compact differential source synchronous receiver PHY comprised of 22 data lanes and 1 clock lane. This receiver, plus a corresponding transmitter and impedance calibration macro, support multiple differential and ground terminated link standards at 4.8 to 6.4Gb/s, such as Intel QPI 1.0 and IBM proprietary memory links.
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