Suppression of flicker noise upconversion in a 65nm CMOS VCO in the 3.0-to-3.6GHz band

Flicker noise up-conversion into close-in 1/f3 phase noise is still one of the major issues in the design of CMOS oscillators. Suppression techniques have been recently presented suggesting (i) adoption of a resonant network [1], (ii) reduction of transistor size [2] or (iii) insertion of source degeneration [3]. However, resonant solutions do not guarantee suppression over a wide frequency range, while the other options affect the oscillator start-up margin and degrade the “white” 1/f2 phase noise. This work presents an alternative technique that does not rely on resonant elements and does not affect both start-up margin and 1/f2 phase noise. Demonstration of the technique is described in a 65nm CMOS VCO design.