2010 IEEE International Solid-State Circuits Conference - (ISSCC)最新文献_第10页

Session 8 overview: High-speed wireline transceivers 第8部分概述:高速有线收发器

2010 IEEE International Solid-State Circuits Conference - (ISSCC) Pub Date : 2010-03-18 DOI: 10.1109/ISSCC.2010.5434012

A. Sheikholeslami, T. Saito

引用次数: 0

A 45nm SOI embedded DRAM macro for POWER7TM 32MB on-chip L3 cache 一个45nm SOI嵌入式DRAM宏，用于POWER7TM 32MB片上L3高速缓存

2010 IEEE International Solid-State Circuits Conference - (ISSCC) Pub Date : 2010-03-18 DOI: 10.1109/ISSCC.2010.5433814

J. Barth, D. Plass, E. Nelson, C. Hwang, G. Fredeman, M. Sperling, A. Mathews, W. Reohr, Kavita Nair, N. Cao

{"title":"A 45nm SOI embedded DRAM macro for POWER7TM 32MB on-chip L3 cache","authors":"J. Barth, D. Plass, E. Nelson, C. Hwang, G. Fredeman, M. Sperling, A. Mathews, W. Reohr, Kavita Nair, N. Cao","doi":"10.1109/ISSCC.2010.5433814","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5433814","url":null,"abstract":"Logic-based embedded DRAM has matured into a wide range of ASIC applications, SRAM replacements [1] and off-chip caches for microprocessors [2]. While embedded DRAM has been leveraged in supercomputers such as IBM's BlueGene/L [3], it's use has been limited to moderate performance bulk logic technologies. Although prototypes have been demonstrated [4], DRAM has yet to be embedded on a high performance microprocessor. This paper discloses an SOI DRAM macro implemented on-chip with the IBM POWER7™ high performance microprocessor [5], and introduces enhancements to the micro sense amp (µSA) architecture [6]. This high performance DRAM macro is used to construct a large 32MB L3 cache on-chip, eliminating delay, area and power from the off-chip interface, simultaneously improving system performance, reducing cost, power and soft error vulnerability. Figure 19.1.1a shows an SEM of the 45nm SOI DRAM Device and Deep Trench (DT) capacitor [7]. DT offers 25x more capacitance than planar structures and was also utilized to reduce on-chip voltage island supply noise.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"60 1","pages":"342-343"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84630398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 33

Compact voltage and current stimulation buffer for high-density microelectrode arrays 用于高密度微电极阵列的紧凑型电压和电流刺激缓冲器

2010 IEEE International Solid-State Circuits Conference - (ISSCC) Pub Date : 2010-03-18 DOI: 10.1109/ISSCC.2010.5433935

P. Livi, F. Heer, U. Frey, D. Bakkum, A. Hierlemann

引用次数: 9

A 16b 250MS/s IF-sampling pipelined A/D converter with background calibration 带有背景校准的16b 250MS/s中频采样流水线A/D转换器

2010 IEEE International Solid-State Circuits Conference - (ISSCC) Pub Date : 2010-03-18 DOI: 10.1109/ISSCC.2010.5433923

Ahmed M. A. Ali, Andrew S. Morgan, C. Dillon, G. Patterson, S. Puckett, M. Hensley, Russell Stop, Paritosh Bhoraskar, S. Bardsley, David Lattimore, Jeff Bray, Carroll Speir, Robert Sneed

引用次数: 46

An 80×60 range image sensor based on 10µm 50MHz lock-in pixels in 0.18µm CMOS 基于0.18µm CMOS中的10µm 50MHz锁定像素的80×60距离图像传感器

2010 IEEE International Solid-State Circuits Conference - (ISSCC) Pub Date : 2010-03-18 DOI: 10.1109/ISSCC.2010.5433980

D. Stoppa, N. Massari, L. Pancheri, M. Malfatti, M. Perenzoni, L. Gonzo

引用次数: 29

A 5Gb/s transceiver with an ADC-based feedforward CDR and CMA adaptive equalizer in 65nm CMOS 5Gb/s收发器，基于adc的前馈CDR和CMA自适应均衡器，采用65nm CMOS

2010 IEEE International Solid-State Circuits Conference - (ISSCC) Pub Date : 2010-03-18 DOI: 10.1109/ISSCC.2010.5434001

H. Yamaguchi, H. Tamura, Y. Doi, Y. Tomita, T. Hamada, M. Kibune, Shuhei Ohmoto, Keita Tateishi, Oleksiy Tyshchenko, A. Sheikholeslami, Tomokazu Higuchi, J. Ogawa, Tamio Saito, H. Ishida, K. Gotoh

{"title":"A 5Gb/s transceiver with an ADC-based feedforward CDR and CMA adaptive equalizer in 65nm CMOS","authors":"H. Yamaguchi, H. Tamura, Y. Doi, Y. Tomita, T. Hamada, M. Kibune, Shuhei Ohmoto, Keita Tateishi, Oleksiy Tyshchenko, A. Sheikholeslami, Tomokazu Higuchi, J. Ogawa, Tamio Saito, H. Ishida, K. Gotoh","doi":"10.1109/ISSCC.2010.5434001","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5434001","url":null,"abstract":"A high bandwidth and a robust performance are demanded in the consumer market applications. An ADC-based transceiver satisfies these demands and enables power/area scaling with process [1,2]. We developed and tested a spread-spectrum-clocking (SSC) compliant 5-Gb/s transceiver in 65-nm CMOS. The receiver uses an ADC-based front-end that samples the incoming signal without adjusting the phase relation between the sampling clock and the signal, hence eliminating the need for phase control of the sampling clock (Fig. 8.7.1). The phase tracking of the incoming signal and the data decision are performed entirely in the numerical domain without generating physical sampling-clock phases. An adaptive digital FFE (feed-forward equalizer) compensates for a channel loss up to 15dB at 2.5 GHz, using an on-chip adaptation controller based on CMA (constant-modulus algorithm). The CDR operated with BER less than 1E-12 when the transmitter and receiver clock signals were independently SSC-modulated at a modulation frequency of 30 kHz with a frequency deviation of 0 to −5000ppm.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":"20 1","pages":"168-169"},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88834840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 33

A 2.4GHz/915MHz 51µW wake-up receiver with offset and noise suppression 2.4GHz/915MHz 51µW唤醒接收器，具有偏移和噪声抑制功能

2010 IEEE International Solid-State Circuits Conference - (ISSCC) Pub Date : 2010-03-18 DOI: 10.1109/ISSCC.2010.5433958

Xiongchuan Huang, Simonetta Rampu, Xiaoyang Wang, G. Dolmans, H. D. Groot

引用次数: 173

A 64Mb MRAM with clamped-reference and adequate-reference schemes 具有箝位参考和充分参考方案的64Mb MRAM

2010 IEEE International Solid-State Circuits Conference - (ISSCC) Pub Date : 2010-03-18 DOI: 10.1109/ISSCC.2010.5433948

K. Tsuchida, T. Inaba, K. Fujita, Y. Ueda, Takafumi Shimizu, Y. Asao, T. Kajiyama, M. Iwayama, K. Sugiura, S. Ikegawa, T. Kishi, T. Kai, M. Amano, N. Shimomura, H. Yoda, Y. Watanabe

引用次数: 205

A 1.296-to-5.184Gb/s Transceiver with 2.4mW/(Gb/s) Burst-mode CDR using Dual-Edge Injection-Locked Oscillator 基于双边缘注入锁定振荡器的1.296 ~ 5.184Gb/s突发模式CDR收发器

2010 IEEE International Solid-State Circuits Conference - (ISSCC) Pub Date : 2010-03-18 DOI: 10.1109/ISSCC.2010.5433821

Kenichi Maruko, Tatsuya Sugioka, H. Hayashi, Zhiwei Zhou, Yasunori Tsukuda, Y. Yagishita, H. Konishi, Toshikyuki Ogata, Hisashi Owa, T. Niki, K. Konda, M. Sato, Hiroshi Shiroshita, Takeshi Ogura, T. Aoki, H. Kihara, Sachiya Tanaka

引用次数: 34

A 0.06mm2 8.9b ENOB 40MS/s pipelined SAR ADC in 65nm CMOS 一个0.06mm2 8.9b ENOB 40MS/s的65nm CMOS流水线SAR ADC

2010 IEEE International Solid-State Circuits Conference - (ISSCC) Pub Date : 2010-03-18 DOI: 10.1109/ISSCC.2010.5433968

M. Furuta, M. Nozawa, T. Itakura

引用次数: 29