Session 8 overview: High-speed wireline transceivers

Abstract

The demand for higher bandwidth in chip-to-chip and backplane communication is driven by the video transmission over the internet. This demand has driven the data rates to 10Gb/s and beyond. Currently, there are two approaches to address the increasing bandwidth requirement for high-speed transceivers: one is to increase the number of parallel lines while maintaining the line rate and the other is to increase the data rate per line while maintaining the number of parallel lines. The former eases the requirement for clock and data recovery, as the clock can be forwarded with small overhead. This is applicable to cases where the channel is short and linear equalization is sufficient to compensate for the channel loss. The latter reduces the number of pins on the chips and reduces the board area at the expense of more complicated equalization scheme and techniques for clock and data recovery (CDR). This is applicable to cases where the channel is long and linear equalization is no longer sufficient.