3.3GHz DCO with a frequency resolution of 150Hz for All-digital PLL

In all-digital phase-locked loops (ADPLLs), the quantization noise introduced by the frequency discretization in the digitally controlled oscillator (DCO) can affect the performance in terms of out-of-band phase noise. In particular, the additional quantization noise has to be kept significantly lower than the intrinsic oscillator phase-noise, mandating a very fine frequency resolution (e.g. less than one kHz in GSM) [1]. Typically, in LC oscillators, the digital tuning is realized using two (or more) capacitor banks for coarse and fine tuning. The first bank is used to compensate process and temperature variation and to select the channel while the second is required for the DCO modulation inside the PLL. Since the coarse tuning range can be several hundred MHz (e.g. 800MHz in GSM [1]), a frequency resolution in the range of kHz can result in unitary elements for the capacitor banks of the order of atto-Farads. Although such values can be achieved by means of capacitive divider networks [2], the sensitivity to mismatches and parasitics of these solutions limit the robustness of the design. Staszewski et al. solved this problem by introducing a dithering of the 3 less significant bits of the DCO frequency control word [1]. This approach reduces considerably the equivalent DCO frequency resolution (from 12kHz to 30Hz) but, as occurs in any ΔΣ data converter, the quantization noise is moved to higher frequencies where generally the phase-noise specifications are more challenging. Due to this problem, the frequency of dithering must be significantly increased (225MHz) to satisfy the emission mask requirements far away from the carrier [1].