2010 IEEE International Solid-State Circuits Conference - (ISSCC)最新文献_第2页

A 20Gb/s 40mW equalizer in 90nm CMOS technology 采用90nm CMOS技术的20Gb/s 40mW均衡器

2010 IEEE International Solid-State Circuits Conference - (ISSCC) Pub Date : 2010-03-18 DOI: 10.1109/ISSCC.2010.5433999

S. Ibrahim, B. Razavi

{"title":"A 20Gb/s 40mW equalizer in 90nm CMOS technology","authors":"S. Ibrahim, B. Razavi","doi":"10.1109/ISSCC.2010.5433999","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5433999","url":null,"abstract":"In order to reduce the pin count of chips and the complexity of the routing on printed-circuit boards and backplanes, it is desirable to replace a large number of parallel channels with a few serial links. Such a transformation can also potentially save significant power because it lowers the number of output drivers while maintaining the I/O voltage swings and termination impedances relatively constant. It is therefore plausible that data rates approaching 20 Gb/s will become common in the near future. At these speeds, the loss of FR4 boards poses a great challenge, requiring heavy equalization. From circuit design point of view, it is simpler to employ linear equalization (in the transmitter and the receiver), but from system design point of view, two serious issues make this approach unattractive: the amplification of crosstalk and the lack of ability to equalize for impedance discontinuities (sharp notches in the channel frequency response). In an optimum, yet practical system, one would place 4 to 5 dB of linear equalization in the transmitter and a similar amount in the receiver, and perform the remaining equalization by means of a decision-feedback equalizer (DFE), thus alleviating both issues.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85798328","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 16

A multistandard multiband mobile TV RF SoC in 65nm CMOS 一种采用65nm CMOS的多标准多频段移动电视射频SoC

2010 IEEE International Solid-State Circuits Conference - (ISSCC) Pub Date : 2010-03-18 DOI: 10.1109/ISSCC.2010.5433847

Jae-Hong Chang, Huijung Kim, Jeong-Hyun Choi, Hangun Chung, Jungwook Heo, Sanghoon Kang, Jong-Dae Bae, Heetae Oh, Youngwoon Kim, T. Kwon, Ryan Kim, Wooseung Choo, D. Rhee, Byeong-ha Park

{"title":"A multistandard multiband mobile TV RF SoC in 65nm CMOS","authors":"Jae-Hong Chang, Huijung Kim, Jeong-Hyun Choi, Hangun Chung, Jungwook Heo, Sanghoon Kang, Jong-Dae Bae, Heetae Oh, Youngwoon Kim, T. Kwon, Ryan Kim, Wooseung Choo, D. Rhee, Byeong-ha Park","doi":"10.1109/ISSCC.2010.5433847","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5433847","url":null,"abstract":"The mobile TV applications such as DVH-H/T, T-DMB/DAB, ISDB-T are recently emerging all over the world. To support various applications, the multistandard and multiband mobile TV RF tuner is developed as a cost-effective and size-effective solution [1]. The demand for smaller form factor and power consumption reduction of RF and Channel is very high, and SoC technology is being adopted to meet the customer's requirements. As shown in Fig. 25.7.1, an SoC that implements all of the standards and frequency bands of a mobile TV in a 65nm CMOS is presented in this paper. This RF SoC consists of three RF front ends, a dual-mode analog baseband filter supporting lowpass filtering and complex bandpass filtering, a digitally controlled programmable-gain amplifier (PGA), wideband VCO/PLL, DCXO, data converters, demodulator, forward error correction (FEC), hardwired multiprotocl encapsulation forward error correction (MPE-FEC), ARM CPU and SRAM. This mobile TV RF SoC reduces board area and complexity while cutting system design time.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72799930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 25

A 2.4GHz 830pJ/bit duty-cycled wake-up receiver with −82dBm sensitivity for crystal-less wireless sensor nodes 2.4GHz 830pJ/bit占空比唤醒接收器，灵敏度为−82dBm，用于无晶无线传感器节点

2010 IEEE International Solid-State Circuits Conference - (ISSCC) Pub Date : 2010-03-18 DOI: 10.1109/ISSCC.2010.5433955

S. Drago, D. Leenaerts, F. Sebastiano, L. Breems, K. Makinwa, B. Nauta

引用次数: 110

A wire-speed powerTM processor: 2.3GHz 45nm SOI with 16 cores and 64 threads 线速powerTM处理器:2.3GHz 45nm SOI, 16核64线程

2010 IEEE International Solid-State Circuits Conference - (ISSCC) Pub Date : 2010-03-18 DOI: 10.1109/ISSCC.2010.5434075

Charles L. Johnson, D. Allen, Jeffrey D. Brown, Steven P. Vanderwiel, R. Hoover, Heather D. Achilles, Chen-Yong Cher, G. May, H. Franke, J. Xenidis, C. Basso

引用次数: 76

A low-noise frequency synthesizer for infrastructure applications 用于基础设施应用的低噪声频率合成器

2010 IEEE International Solid-State Circuits Conference - (ISSCC) Pub Date : 2010-03-18 DOI: 10.1109/ISSCC.2010.5433944

S. Farahvash, W. Roberts, Jake Easter, R. Wei, D. Stegmeir, Li Jin

引用次数: 1

A 2.1Mpixel 120frame/s CMOS image sensor with column-parallel ΔΣ ADC architecture 采用柱并行ΔΣ ADC架构的2.1Mpixel 120frame/s CMOS图像传感器

2010 IEEE International Solid-State Circuits Conference - (ISSCC) Pub Date : 2010-03-18 DOI: 10.1109/ISSCC.2010.5433974

Youngcheol Chae, Jimin Cheon, Seung-hyun Lim, Dongmyung Lee, Minho Kwon, Kwi-sung Yoo, Wun-ki Jung, Dong-Hun Lee, S. Ham, G. Han

{"title":"A 2.1Mpixel 120frame/s CMOS image sensor with column-parallel ΔΣ ADC architecture","authors":"Youngcheol Chae, Jimin Cheon, Seung-hyun Lim, Dongmyung Lee, Minho Kwon, Kwi-sung Yoo, Wun-ki Jung, Dong-Hun Lee, S. Ham, G. Han","doi":"10.1109/ISSCC.2010.5433974","DOIUrl":"https://doi.org/10.1109/ISSCC.2010.5433974","url":null,"abstract":"Over the last few years, the demands for high-density and high-speed imaging have increased drastically. Since CMOS image sensors have the advantages of low power consumption and easy system integration, they have become dominant over CCDs in the consumer market [1–4]. A column-parallel ADC architecture is the most widely used ADC in CMOS image sensors for high-speed and low-power operation [2–6]. The column-parallel architecture can be classified as: successive-approximation register (SAR) [2], cyclic [3], single-slope (SS) [4], and delta-sigma (ΔΣ) [5,6] ADCs. Although SAR ADCs have been utilized for high-speed imaging, such as UDTV, they require a DAC in a column, whose area is unacceptably large for consumer electronics with a fine pixel pitch. Cyclic ADCs have also been reported in high-speed imaging, but they have high power consumption and high noise levels. Since SS ADCs provide relatively high resolution with minimum area, they have been widely used in CMOS image sensors. However, SS ADCs require very fast clock signals leading to high power consumption in the case of high-speed imaging. Although ΔΣ ADCs have been investigated for low-noise imaging, they have only been applied for low-speed imaging with large pixel pitch because of the complexity of ΔΣ modulators and following decimation filters.","PeriodicalId":6418,"journal":{"name":"2010 IEEE International Solid-State Circuits Conference - (ISSCC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2010-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86444995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 101

A 12.3mW 12.5Gb/s complete transceiver in 65nm CMOS 一个采用65nm CMOS的12.3mW 12.5Gb/s完整收发器

2010 IEEE International Solid-State Circuits Conference - (ISSCC) Pub Date : 2010-03-18 DOI: 10.1109/ISSCC.2010.5433824

Koji Fukuda, H. Yamashita, G. Ono, R. Nemoto, Eiichi Suzuki, T. Takemoto, F. Yuki, T. Saito

引用次数: 42

SRAM stability characterization using tunable ring oscillators in 45nm CMOS 在45nm CMOS中使用可调谐环形振荡器的SRAM稳定性表征

2010 IEEE International Solid-State Circuits Conference - (ISSCC) Pub Date : 2010-03-18 DOI: 10.1109/ISSCC.2010.5433820

Jason Tsai, S. Toh, Z. Guo, L. Pang, T. Liu, B. Nikolić

引用次数: 18

A 2.2/3-inch 4K2K CMOS image sensor based on dual resolution and exposure technique 一种基于双分辨率曝光技术的2.2/3英寸4K2K CMOS图像传感器

2010 IEEE International Solid-State Circuits Conference - (ISSCC) Pub Date : 2010-03-18 DOI: 10.1109/ISSCC.2010.5433977

Takeo Azuma, T. Imagawa, Sanzo Ugawa, Yusuke Okada, H. Komobuchi, M. Ishii, S. Kasuga, Y. Kato

引用次数: 5

The implementation of POWER7TM: A highly parallel and scalable multi-core high-end server processor POWER7TM的实现:一个高度并行和可伸缩的多核高端服务器处理器

2010 IEEE International Solid-State Circuits Conference - (ISSCC) Pub Date : 2010-03-18 DOI: 10.1109/ISSCC.2010.5434074

D. Wendel, R. Kalla, Robert Cargnoni, J. Clabes, J. Friedrich, R. Frech, J. Kahle, B. Sinharoy, William J. Starke, Scott A. Taylor, S. Weitzel, S. Chu, M. S. Islam, V. Zyuban

引用次数: 83