2013 IEEE International Test Conference (ITC)最新文献_第3页

High sensitivity test signatures for unconventional analog circuit test paradigms 用于非常规模拟电路测试范例的高灵敏度测试签名

2013 IEEE International Test Conference (ITC) Pub Date : 2013-11-04 DOI: 10.1109/TEST.2013.6651884

S. Sindia, V. Agrawal

{"title":"High sensitivity test signatures for unconventional analog circuit test paradigms","authors":"S. Sindia, V. Agrawal","doi":"10.1109/TEST.2013.6651884","DOIUrl":"https://doi.org/10.1109/TEST.2013.6651884","url":null,"abstract":"A method of testing for parametric faults in analog circuits based on a polynomial representation of fault-free function of the circuit is presented. The response of the circuit under test (CUT) is estimated as a polynomial in the root mean square (RMS) magnitude of the applied input voltage at a relevant frequency or DC. The test then classifies the CUT as fault-free or faulty based upon a comparison of the estimated polynomial coefficients with those of the fault-free circuit. The test application needs very little augmentation of the circuit to make it testable as only output parameters are used for classification. The method is validated on an active elliptic filter and is shown to uncover parametric faults causing deviations as small as 5% from nominal values. Fault diagnosis based upon sensitivity of polynomial coefficients at relevant frequencies is discussed. Another type of circuit signatures in the form of probability moments of the output when test input is random noise are also proposed. It is shown that the sensitivity of either signature can be enhanced by a newly proposed nonlinear V-transform. Finally, an adaptive test framework leveraging from these signatures and the transform technique is shown to improve defect level and yield loss.","PeriodicalId":6379,"journal":{"name":"2013 IEEE International Test Conference (ITC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81312920","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

A graph-theoretic approach for minimizing the number of wrapper cells for pre-bond testing of 3D-stacked ICs 最小化3d堆叠集成电路键前测试封装单元数量的图论方法

2013 IEEE International Test Conference (ITC) Pub Date : 2013-11-04 DOI: 10.1109/TEST.2013.6651895

Mukesh Agrawal, K. Chakrabarty

{"title":"A graph-theoretic approach for minimizing the number of wrapper cells for pre-bond testing of 3D-stacked ICs","authors":"Mukesh Agrawal, K. Chakrabarty","doi":"10.1109/TEST.2013.6651895","DOIUrl":"https://doi.org/10.1109/TEST.2013.6651895","url":null,"abstract":"Three-dimensional (3D) stacking of ICs using through-silicon-vias (TSVs) is a promising integration platform for next-generation ICs. Since TSVs are not fully accessible prior to bonding, it is difficult to test the combinational logic between scan flip-flops and TSVs at a pre-bond stage. In order to increase testability, it has been advocated that wrapper cells be added at both ends of a TSV. However, a drawback of wrapper cells is that they incur area overhead and lead to higher latency and performance degradation on functional paths. Prior work proposed the reuse of scan cells to achieve high testability, thereby reducing the number of wrapper cells that need to be inserted; however, practical timing considerations were overlooked and the number of inserted wrapper cells was still high. We show that the general problem of minimizing the wrapper cells is equivalent to the graph-theoretic minimum clique-partitioning problem, and is therefore NP-hard. We adopt efficient heuristic methods to solve the problem and describe a timing-guided and layout-aware solution. We also evaluate the heuristic methods using an exact solution technique based on integer linear programming. Results are presented for 3D-stack implementations of the ITC'99 and the OpenCore benchmark circuits.","PeriodicalId":6379,"journal":{"name":"2013 IEEE International Test Conference (ITC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83525011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

The implementation and application of a protocol aware architecture 协议感知体系结构的实现和应用

2013 IEEE International Test Conference (ITC) Pub Date : 2013-11-04 DOI: 10.1109/TEST.2013.6651911

T. Lyons, George Conner, J. Aslanian, Shawn Sullivan

引用次数: 0

On the reuse of read and write assist circuits to improve test efficiency in low-power SRAMs 读写辅助电路的复用以提高低功耗sram的测试效率

2013 IEEE International Test Conference (ITC) Pub Date : 2013-11-04 DOI: 10.1109/TEST.2013.6651927

L. Zordan, A. Bosio, L. Dilillo, P. Girard, A. Todri, A. Virazel, N. Badereddine

{"title":"On the reuse of read and write assist circuits to improve test efficiency in low-power SRAMs","authors":"L. Zordan, A. Bosio, L. Dilillo, P. Girard, A. Todri, A. Virazel, N. Badereddine","doi":"10.1109/TEST.2013.6651927","DOIUrl":"https://doi.org/10.1109/TEST.2013.6651927","url":null,"abstract":"Read and write assist techniques are widely adopted to allow voltage scaling in low-power SRAMs. In particular, this paper analyzes two assist techniques: word line level reduction and negative bit line boost. The analyzed assist techniques improve read stability and write margin of core-cells when the SRAM operates at a lowered supply voltage. In this work, we investigate the impact of such assist techniques on the faulty behavior of low-power SRAMs. This analysis is based on extensive injection of resistive-open and resistive-bridging defects in core-cells of a commercial low-power SRAM. Our study determines the most stressful configuration of assist circuits to detect each faulty behavior induced by injected defects. We show that, by applying most stressful configurations of assist circuits during test phase, defect coverage can be increased up to 89% w.r.t. test solutions that do not exploit assist circuits. Based on this analysis, we present an efficient test solution that exploits the configuration of assist circuits as a parameter to maximize the detection of studied defects, while reducing time complexity up to 73% w.r.t. test flows using state-of-the-art test algorithms.","PeriodicalId":6379,"journal":{"name":"2013 IEEE International Test Conference (ITC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79234286","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Representative critical-path selection for aging-induced delay monitoring 老化延迟监测中具有代表性的关键路径选择

2013 IEEE International Test Conference (ITC) Pub Date : 2013-11-04 DOI: 10.1109/TEST.2013.6651924

F. Firouzi, Fangming Ye, K. Chakrabarty, M. Tahoori

引用次数: 40

Early-life-failure detection using SAT-based ATPG 基于sat的ATPG早期寿命失效检测

2013 IEEE International Test Conference (ITC) Pub Date : 2013-11-04 DOI: 10.1109/TEST.2013.6651925

M. Sauer, Young Moon Kim, Jun Seomun, Hyung-Ock Kim, K. Do, J. Choi, Kee-sup Kim, S. Mitra, B. Becker

{"title":"Early-life-failure detection using SAT-based ATPG","authors":"M. Sauer, Young Moon Kim, Jun Seomun, Hyung-Ock Kim, K. Do, J. Choi, Kee-sup Kim, S. Mitra, B. Becker","doi":"10.1109/TEST.2013.6651925","DOIUrl":"https://doi.org/10.1109/TEST.2013.6651925","url":null,"abstract":"Early-life failures (ELF) result from weak chips that may pass manufacturing tests but fail early in the field, much earlier than expected product lifetime. Recent experimental studies over a range of technologies have demonstrated that ELF defects result in changes in delays over time inside internal nodes of a logic circuit before functional failure occurs. Such changes in delays are distinct from delay degradation caused by circuit aging mechanisms such as Bias Temperature Instability. Traditional transition fault or robust path delay fault test patterns are inadequate for detecting such ELF-induced changes in delays because they do not model the demanding detection conditions precisely. In this paper, we present an automatic test pattern generation (ATPG) technique based on Boolean Satisfiability (SAT) for detecting ELF-induced delay changes at all gates in a given circuit. Our simulation results, using various circuit blocks from the industrial OpenSPARC T2 design as well as standard benchmarks, demonstrate the effectiveness and practicality of our approach in achieving high coverage of ELF-induced delay change detection. We also demonstrate the robustness of our approach to manufacturing process variations.","PeriodicalId":6379,"journal":{"name":"2013 IEEE International Test Conference (ITC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73865667","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 17

VLSI testing based security metric for IC camouflaging 基于VLSI测试的集成电路伪装安全度量

2013 IEEE International Test Conference (ITC) Pub Date : 2013-11-04 DOI: 10.1109/TEST.2013.6651879

Jeyavijayan Rajendran, O. Sinanoglu, R. Karri

引用次数: 42

Differential scan-path: A novel solution for secure design-for-testability 差分扫描路径:可测试性安全设计的新解决方案

2013 IEEE International Test Conference (ITC) Pub Date : 2013-11-04 DOI: 10.1109/TEST.2013.6651902

S. Manich, Markus S. Wamser, O. Guillen, G. Sigl

引用次数: 3

Predicting system-level test and in-field customer failures using data mining 使用数据挖掘预测系统级测试和现场客户故障

2013 IEEE International Test Conference (ITC) Pub Date : 2013-11-04 DOI: 10.1109/TEST.2013.6651892

Harry H. Chen, R. Hsu, PaulYoung Yang, J. Shyr

引用次数: 29

Fault modeling and diagnosis for nanometric analog circuits 纳米模拟电路的故障建模与诊断

2013 IEEE International Test Conference (ITC) Pub Date : 2013-11-04 DOI: 10.1109/TEST.2013.6651886

K. Huang, H. Stratigopoulos, S. Mir

引用次数: 3