2013 IEEE International Test Conference (ITC)最新文献

Self-repair of uncore components in robust system-on-chips: An OpenSPARC T2 case study 在健壮的片上系统中非核心组件的自我修复:一个OpenSPARC T2案例研究

2013 IEEE International Test Conference (ITC) Pub Date : 2013-11-04 DOI: 10.1109/TEST.2013.6651907

Yanjing Li, E. Cheng, S. Makar, S. Mitra

{"title":"Self-repair of uncore components in robust system-on-chips: An OpenSPARC T2 case study","authors":"Yanjing Li, E. Cheng, S. Makar, S. Mitra","doi":"10.1109/TEST.2013.6651907","DOIUrl":"https://doi.org/10.1109/TEST.2013.6651907","url":null,"abstract":"Self-repair replaces/bypasses faulty components in a system-on-chip (SoC) to keep the system functioning correctly even in the presence of permanent faults. Such faults may result from early-life failures, circuit aging, and manufacturing defects and variations. Unlike on-chip memories, processor cores, and networks-on-chip, little attention has been paid to self-repair of uncore components (e.g., cache controllers, memory controllers, and I/O controllers) that occupy significant portions of multi-core SoCs. In this paper, we present new techniques that utilize architectural features to achieve self-repair of uncore components while incurring low area, power, and performance costs. We demonstrate the effectiveness and practicality of our techniques, using the industrial OpenSPARC T2 SoC with 8 processor cores that support 64 hardware threads. Our key results are: 1. Our techniques enable effective self-repair of any single faulty uncore component with 7.5% post-layout chip-level area impact and 3% power impact. In contrast, existing redundancy techniques impose high (e.g., 16%) area costs. Our techniques do not incur any performance impact in fault-free systems. In the presence of a single faulty uncore component, there can be a 5% application performance impact. 2. Our techniques are capable of self-repairing multiple faulty uncore components without any additional area impact, but with graceful degradation of application performance. 3. Our techniques achieve high self-repair coverage of 97.5% in the presence of a single fault. Our self-repair techniques also enable flexible tradeoffs between self-repair coverage and area costs. For example, 75% self-repair coverage can be achieved with 3.2% post-layout chip-level area impact.","PeriodicalId":6379,"journal":{"name":"2013 IEEE International Test Conference (ITC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75053340","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 26

Theory, model, and applications of non-Gaussian probability density functions for random jitter/noise with non-white power spectral densities 非白功率谱密度随机抖动/噪声的非高斯概率密度函数的理论、模型和应用

2013 IEEE International Test Conference (ITC) Pub Date : 2013-11-04 DOI: 10.1109/TEST.2013.6651910

Daniel Chow, Masashi Shimanouchi, Mike P. Li

引用次数: 0

AgentDiag: An agent-assisted diagnostic framework for board-level functional failures AgentDiag:用于董事会级功能故障的代理辅助诊断框架

2013 IEEE International Test Conference (ITC) Pub Date : 2013-11-04 DOI: 10.1109/TEST.2013.6651918

Zelong Sun, Li Jiang, Q. Xu, Zhaobo Zhang, Zhiyuan Wang, Xinli Gu

引用次数: 13

A novel test structure for measuring the threshold voltage variance in MOSFETs 一种用于测量mosfet阈值电压方差的新型测试结构

2013 IEEE International Test Conference (ITC) Pub Date : 2013-11-04 DOI: 10.1109/TEST.2013.6651878

Takahiro J. Yamaguchi, James S. Tandon, S. Komatsu, K. Asada

引用次数: 8

FPGA-based universal embedded digital instrument 基于fpga的通用嵌入式数字仪表

2013 IEEE International Test Conference (ITC) Pub Date : 2013-11-04 DOI: 10.1109/TEST.2013.6651917

J. Ferry

引用次数: 7

A distributed-multicore hybrid ATPG system 分布式多核混合ATPG系统

2013 IEEE International Test Conference (ITC) Pub Date : 2013-11-04 DOI: 10.1109/TEST.2013.6651916

X. Cai, P. Wohl

引用次数: 13

BA-BIST: Board test from inside the IC out BA-BIST:从IC内到外的电路板测试

2013 IEEE International Test Conference (ITC) Pub Date : 2013-11-04 DOI: 10.1109/TEST.2013.6651919

Z. Conroy, A. Crouch

引用次数: 2

RF MEMS switches for Wide I/O data bus applications 用于宽I/O数据总线应用的RF MEMS开关

2013 IEEE International Test Conference (ITC) Pub Date : 2013-11-04 DOI: 10.1109/TEST.2013.6651889

M. Cohn, Kaosio Saechao, Michael Whitlock, Daniel Brenman, Wallace T. Tang, R. Proie

引用次数: 11

Performance enhancement of a WCDMA/HSDPA+ receiver via minimizing error vector magnitude 通过最小化误差矢量来增强WCDMA/HSDPA+接收机的性能

2013 IEEE International Test Conference (ITC) Pub Date : 2013-11-04 DOI: 10.1109/TEST.2013.6651881

Wei Gao, Chris Liu

引用次数: 1

Process monitoring through wafer-level spatial variation decomposition 通过晶圆级空间变异分解进行过程监控

2013 IEEE International Test Conference (ITC) Pub Date : 2013-11-04 DOI: 10.1109/TEST.2013.6651901

K. Huang, Nathan Kupp, J. Carulli, Y. Makris

{"title":"Process monitoring through wafer-level spatial variation decomposition","authors":"K. Huang, Nathan Kupp, J. Carulli, Y. Makris","doi":"10.1109/TEST.2013.6651901","DOIUrl":"https://doi.org/10.1109/TEST.2013.6651901","url":null,"abstract":"Monitoring the semiconductor manufacturing process and understanding the various sources of variation and their repercussions is a crucial capability. Indeed, identifying the root-cause of device failures, enhancing yield of future production through improvement of the manufacturing environment, and providing feedback to the designer toward development of design techniques that minimize failure rate rely on such a capability. To this end, we introduce a spatial decomposition method for breaking down the variation of a wafer to its spatial constituents, based on a small number of measurements sampled across the wafer. We demonstrate that by leveraging domain-specific knowledge and by using as constituents dynamically learned, interpretable basis functions, the ability of the proposed method to accurately identify the sources of variation is drastically improved, as compared to existing approaches. We then illustrate the utility of the proposed spatial variation decomposition method in (i) identifying the main contributor to yield variation, (ii) predicting the actual yield of a wafer, and (iii) clustering wafers for production planning and abnormal wafer identification purposes. Results are reported on industrial data from high-volume manufacturing, confirming the ability of the proposed method to provide great insight regarding the sources of variation in the semiconductor manufacturing process.","PeriodicalId":6379,"journal":{"name":"2013 IEEE International Test Conference (ITC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81109758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12