{"title":"An enhanced procedure for calculating dynamic properties of high-performance DAC on ATE","authors":"Ming-Hsien Lu","doi":"10.1109/TEST.2013.6651877","DOIUrl":"https://doi.org/10.1109/TEST.2013.6651877","url":null,"abstract":"Due to the current hardware and testing environment limitations, sometimes a perfect coherent condition cannot be satisfied regarding Digital-to-Analog Converter testing. In this paper, the existing algorithms for non-coherent sampling are reviewed and the limitations of each algorithm are analyzed. Then an enhanced procedure is proposed with detail explanation. The experimental results show the new procedure has a higher accuracy and a broader coverage.","PeriodicalId":6379,"journal":{"name":"2013 IEEE International Test Conference (ITC)","volume":"8 1","pages":"1-10"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82559939","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"ATE test time reduction using asynchronous clock period","authors":"P. Venkataramani, V. Agrawal","doi":"10.1109/TEST.2013.6651931","DOIUrl":"https://doi.org/10.1109/TEST.2013.6651931","url":null,"abstract":"A conventional wafer sort test on an automatic test equipment (ATE) uses a fixed synchronous clock period. Typical test cycles may produce high signal activity and to keep the power dissipation under control, a relatively slow test clock is used. This results in long test times, especially for large scan based circuits. Observing that each test clock cycle may consume different amount of power, we propose an asynchronous clock test methodology to reduce the test time. Smallest customized clock periods for test cycles or sets of cycles are computed based on power and critical path constraints. A theoretical analysis shows that the total energy consumed by the entire test is invariant and the test time depends on the rate it is dissipated during test. An asynchronous clock test dissipates this energy at the maximum allowable rate, while the conventional synchronous clock test dissipates it at a lower average rate. The asynchronous clock test method is first implemented in simulation using several ISCAS'89 benchmark circuits. These results show test time reductions up to 47%. To establish the test programming feasibility of the new methodology the Advantest T2000GS ATE at Auburn University Test Lab was used. Test time reduction of 38% is demonstrated for scan test of a circuit. The paper ends with an investigation showing that for a circuit under test, given its power budget and a test there exists a supply voltage that minimizes the test time. An analysis determines whether the shortest test must use a synchronous or an asynchronous clock.","PeriodicalId":6379,"journal":{"name":"2013 IEEE International Test Conference (ITC)","volume":"27 1","pages":"1-10"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80751556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Sen-Kuei Hsu, Hao Chen, Chung-Han Huang, Der-Jiann Liu, Wei-Hsun Lin, Hung-Chih Lin, C. Peng, Min-Jer Wang
{"title":"Test-yield improvement of high-density probing technology using optimized metal backer with plastic patch","authors":"Sen-Kuei Hsu, Hao Chen, Chung-Han Huang, Der-Jiann Liu, Wei-Hsun Lin, Hung-Chih Lin, C. Peng, Min-Jer Wang","doi":"10.1109/TEST.2013.6651888","DOIUrl":"https://doi.org/10.1109/TEST.2013.6651888","url":null,"abstract":"High-density probing is a main trend of the test technology. The warping issues of probe card are caused by the high-density test. The metal backer and patches are applied to solve this problem and the optimized sizes of backer and patches are decided by the proposed flow. Using the probe card with optimized backer and patches, the stability of test can be ensured and the test yields are increased. 26.56% test-yield improvement can be obtained.","PeriodicalId":6379,"journal":{"name":"2013 IEEE International Test Conference (ITC)","volume":"5 1","pages":"1-10"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89139320","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
P. Wohl, J. Waicukauski, Frederic Neuveux, Gregory A. Maston, Nadir Achouri, J. E. Colburn
{"title":"Two-level compression through selective reseeding","authors":"P. Wohl, J. Waicukauski, Frederic Neuveux, Gregory A. Maston, Nadir Achouri, J. E. Colburn","doi":"10.1109/TEST.2013.6651896","DOIUrl":"https://doi.org/10.1109/TEST.2013.6651896","url":null,"abstract":"As scan compression becomes ubiquitous, ever more complex designs require higher compression. This paper presents a novel, two-level compression system for scan input data generated by deterministic test generation. First, load care bits and X-control input data are encoded into PRPG seeds; next, seeds are selectively shared for further compression. The latter exploits the hierarchical nature of large designs with tens or hundreds of PRPGs. The system comprises a new architecture, which includes a simple instruction-decode unit, and new algorithms embedded into ATPG. Results on large industrial designs demonstrate significant data and cycle compression increases while maintaining test coverage and performance.","PeriodicalId":6379,"journal":{"name":"2013 IEEE International Test Conference (ITC)","volume":"301 1","pages":"1-10"},"PeriodicalIF":0.0,"publicationDate":"2013-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85578754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A test probe for TSV using resonant inductive coupling","authors":"R. Rashidzadeh, I. Basith","doi":"10.1109/itc.2013.6861555","DOIUrl":"https://doi.org/10.1109/itc.2013.6861555","url":null,"abstract":"A contactless TSV probe based on the principle of resonant inductive coupling is presented in this work. The proposed scheme allows TSV data observation up to 2Gbps when the probe and TSV are 15μm apart.","PeriodicalId":6379,"journal":{"name":"2013 IEEE International Test Conference (ITC)","volume":"56 1","pages":"1-6"},"PeriodicalIF":0.0,"publicationDate":"2013-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72739394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}