2013 IEEE International Test Conference (ITC)最新文献_第5页

SCAN-PUF: A low overhead Physically Unclonable Function from scan chain power-up states scan - puf:扫描链上电状态的低开销物理不可克隆函数

2013 IEEE International Test Conference (ITC) Pub Date : 2013-09-01 DOI: 10.1109/TEST.2013.6651904

Ben Niewenhuis, R. D. Blanton, M. Bhargava, K. Mai

引用次数: 17

Design rule check on the clock gating logic for testability and beyond 设计规则检查时钟门控逻辑的可测试性和超越

2013 IEEE International Test Conference (ITC) Pub Date : 2013-09-01 DOI: 10.1109/TEST.2013.6651930

Kun-Han Tsai, S. Sheng

引用次数: 6

A functional test of 2-GHz/4-GHz RF digital communication device using digital tester 利用数字测试仪对2-GHz/4-GHz射频数字通信设备进行了功能测试

2013 IEEE International Test Conference (ITC) Pub Date : 2013-09-01 DOI: 10.1109/TEST.2013.6651909

K. Ichiyama, M. Ishida, Kenichi Nagatani, Toshifumi Watanabe

引用次数: 5

Zero-overhead self test and calibration of RF transceivers 射频收发器的零开销自检和校准

2013 IEEE International Test Conference (ITC) Pub Date : 2013-09-01 DOI: 10.1109/TEST.2013.6651921

A. Nassery, J. Jeong, S. Ozev

引用次数: 7

Advanced method to refine waveform smeared by jitter in waveform sampler measurement 一种改进波形采样器测量中抖动干扰波形的方法

2013 IEEE International Test Conference (ITC) Pub Date : 2013-09-01 DOI: 10.1109/TEST.2013.6651883

H. Okawara

{"title":"Advanced method to refine waveform smeared by jitter in waveform sampler measurement","authors":"H. Okawara","doi":"10.1109/TEST.2013.6651883","DOIUrl":"https://doi.org/10.1109/TEST.2013.6651883","url":null,"abstract":"Mixed signal ATE (Automated Test Equipment) often integrates a waveform sampler for testing UHF signals. While performing under-sampling, slow jitter greatly influences the captured signal which is reconstructed into a meaningful waveform by manner of coherent waveform reconstruction. The purpose of this work is to remove slow jitter effects from a high-speed digital signal measured by a waveform sampler and to reconstruct a clear waveform and eye pattern. The test signal is a PRBS (Pseudo Random Binary Sequence) bit stream with slow jitter. The PRBS signal becomes an extreme wideband multi-tone from a spectrum point of view, so capturing such a signal with a waveform sampler needs a carefully organized test plan based on the coherent condition. Measured data is reconstructed into a meaningful waveform by reshuffling the sequence of the sampled points. Jitter in the signal is a kind of PM (Phase Modulation) which smears the spectrum. So the point of processing is to demodulate the PM signal and then restore the original multi-tone components. An elegant mathematical equation is introduced to perform the carrier tone recovery. Because of the multi-tone structure, processing needs to be applied to each one of the tone components. First, the PM effect is removed from each tone, and then each tone needs to be compensated amplitude loss by referencing the original tone power. Finally processing successfully reconstructs a clear PRBS waveform and a big eye opening. This paper reports the signal processing in detail with showing 7 Gbps 127-bit PRBS waveform.","PeriodicalId":6379,"journal":{"name":"2013 IEEE International Test Conference (ITC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79000831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

EDT bandwidth management - Practical scenarios for large SoC designs EDT带宽管理-大型SoC设计的实际场景

2013 IEEE International Test Conference (ITC) Pub Date : 2013-09-01 DOI: 10.1109/TEST.2013.6651898

Jakub Janicki, J. Tyszer, Wu-Tung Cheng, Yu Huang, M. Kassab, N. Mukherjee, J. Rajski, Yan Dong, G. Giles

引用次数: 19

30-Gb/s optical and electrical test solution for high-volume testing 30gb /s光电测试解决方案，适合大批量测试

2013 IEEE International Test Conference (ITC) Pub Date : 2013-09-01 DOI: 10.1109/TEST.2013.6651887

D. Watanabe, S. Masuda, H. Hara, T. Ataka, A. Seki, A. Ono, T. Okayasu

引用次数: 11

A design-for-reliability approach based on grading library cells for aging effects 一种基于老化效应分级库单元的可靠性设计方法

2013 IEEE International Test Conference (ITC) Pub Date : 2013-09-01 DOI: 10.1109/TEST.2013.6651923

S. Arasu, M. Nourani, J. Carulli, K. Butler, V. Reddy

引用次数: 8

ATE test time reduction using asynchronous clock period 使用异步时钟周期减少ATE测试时间

2013 IEEE International Test Conference (ITC) Pub Date : 2013-09-01 DOI: 10.1109/TEST.2013.6651931

P. Venkataramani, V. Agrawal

{"title":"ATE test time reduction using asynchronous clock period","authors":"P. Venkataramani, V. Agrawal","doi":"10.1109/TEST.2013.6651931","DOIUrl":"https://doi.org/10.1109/TEST.2013.6651931","url":null,"abstract":"A conventional wafer sort test on an automatic test equipment (ATE) uses a fixed synchronous clock period. Typical test cycles may produce high signal activity and to keep the power dissipation under control, a relatively slow test clock is used. This results in long test times, especially for large scan based circuits. Observing that each test clock cycle may consume different amount of power, we propose an asynchronous clock test methodology to reduce the test time. Smallest customized clock periods for test cycles or sets of cycles are computed based on power and critical path constraints. A theoretical analysis shows that the total energy consumed by the entire test is invariant and the test time depends on the rate it is dissipated during test. An asynchronous clock test dissipates this energy at the maximum allowable rate, while the conventional synchronous clock test dissipates it at a lower average rate. The asynchronous clock test method is first implemented in simulation using several ISCAS'89 benchmark circuits. These results show test time reductions up to 47%. To establish the test programming feasibility of the new methodology the Advantest T2000GS ATE at Auburn University Test Lab was used. Test time reduction of 38% is demonstrated for scan test of a circuit. The paper ends with an investigation showing that for a circuit under test, given its power budget and a test there exists a supply voltage that minimizes the test time. An analysis determines whether the shortest test must use a synchronous or an asynchronous clock.","PeriodicalId":6379,"journal":{"name":"2013 IEEE International Test Conference (ITC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80751556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 10

An enhanced procedure for calculating dynamic properties of high-performance DAC on ATE 在ATE上计算高性能DAC动态特性的增强程序

2013 IEEE International Test Conference (ITC) Pub Date : 2013-09-01 DOI: 10.1109/TEST.2013.6651877

Ming-Hsien Lu

引用次数: 0