2013 IEEE International Test Conference (ITC)最新文献_第4页

In-system diagnosis of RF ICs for tolerance against on-chip in-band interferers 射频集成电路对片上带内干扰容忍度的系统诊断

2013 IEEE International Test Conference (ITC) Pub Date : 2013-11-04 DOI: 10.1109/TEST.2013.6651922

N. Azuma, T. Makita, S. Ueyama, M. Nagata, Satoru Takahashi, M. Murakami, K. Hori, Satoshi Tanaka, M. Yamaguchi

{"title":"In-system diagnosis of RF ICs for tolerance against on-chip in-band interferers","authors":"N. Azuma, T. Makita, S. Ueyama, M. Nagata, Satoru Takahashi, M. Murakami, K. Hori, Satoshi Tanaka, M. Yamaguchi","doi":"10.1109/TEST.2013.6651922","DOIUrl":"https://doi.org/10.1109/TEST.2013.6651922","url":null,"abstract":"The tolerance of RF ICs against on-chip in-band interferers is diagnosed from the viewpoints of the quality of wireless channels compliant with LTE standards. The on-chip interferers inevitably propagate from other active circuits like digital backend processors through silicon substrate coupling in the same die of system-level integration. An in-system diagnosis platform of RF ICs presented in this paper relates the impacts of such interferers on the circuit-level response and system-level communication performance metrics. The figures of communication quality at a system level, like EVM, BER and throughput are concurrently evaluated with the strengths of interferers in different forms and at different locations in a silicon chip. The interferers are measured as the in-band signal to spurious power ratio at the output of RF ICs, the magnitude of substrate voltage fluctuations at the proximity of RF ICs, and related with the amount of power current consumed by base-band digital ICs. The tolerance of RF ICs is represented by the maximum strength of on-chip interferers for sustaining prescribed communication performance. The diagnosis system is divided into two parts, (i) a system-level RF simulator handling modulation and demodulation of real communication vectors in LTE format and also enabling hardware connectivity with RF ICs, and (ii) a silicon emulator of on-chip interferers coupled to the RF ICs. A 65 nm CMOS chip incorporates an on-chip arbitrary noise generator, an on-chip waveform capture, and RF IC for LTE receiver front end, and demonstrates the entire diagnosis.","PeriodicalId":6379,"journal":{"name":"2013 IEEE International Test Conference (ITC)","volume":"65 1","pages":"1-9"},"PeriodicalIF":0.0,"publicationDate":"2013-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72817879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 26

PADRE: Physically-Aware Diagnostic Resolution Enhancement 物理感知诊断分辨率增强

2013 IEEE International Test Conference (ITC) Pub Date : 2013-11-04 DOI: 10.1109/TEST.2013.6651899

Yang Xue, O. Poku, Xin Li, Shawn Blanton

{"title":"PADRE: Physically-Aware Diagnostic Resolution Enhancement","authors":"Yang Xue, O. Poku, Xin Li, Shawn Blanton","doi":"10.1109/TEST.2013.6651899","DOIUrl":"https://doi.org/10.1109/TEST.2013.6651899","url":null,"abstract":"Diagnosis is the first step of IC failure analysis. The conventional objective of identifying the failure locations has been augmented with various physically-aware techniques that are intended to improve both diagnostic resolution and accuracy. Despite these advances, it is often the case however that resolution, i.e., the number of locations or candidates reported by diagnosis, exceeds the number of actual failing locations. Imperfect resolution greatly hinders any follow-on, information-extraction analyses (e.g., physical failure analysis, volume diagnosis, etc.) due to the resulting ambiguity. To address this major challenge, a novel, unsupervised learning methodology that uses ordinarily-available tester and simulation data is described that significantly improves resolution with virtually no negative impact on accuracy. Simulation experiments using a variety of fault types (SSL, MSL, bridges, opens and cell-level input-pattern faults) reveal that the number of failed ICs that have perfect resolution can be more than doubled, and overall resolution is improved by 22%. Application to silicon data also demonstrates significant improvement in resolution (38% overall and the number of chips with ideal resolution is nearly tripled) and verification using PFA demonstrates that accuracy is maintained.","PeriodicalId":6379,"journal":{"name":"2013 IEEE International Test Conference (ITC)","volume":"50 1","pages":"1-10"},"PeriodicalIF":0.0,"publicationDate":"2013-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87613030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 30

Delay testing and characterization of post-bond interposer wires in 2.5-D ICs 2.5 d集成电路中键后中间线的延迟测试和表征

2013 IEEE International Test Conference (ITC) Pub Date : 2013-09-01 DOI: 10.1109/TEST.2013.6651906

Shi-Yu Huang, Li-Ren Huang, Kun-Han Tsai, Wu-Tung Cheng

引用次数: 21

Fault mitigation strategies for CUDA GPUs CUDA gpu的故障缓解策略

2013 IEEE International Test Conference (ITC) Pub Date : 2013-09-01 DOI: 10.1109/TEST.2013.6651908

S. Carlo, Giulio Gambardella, Ippazio Martella, P. Prinetto, Daniele Rolfo, Pascal Trotta

引用次数: 19

Accurate full spectrum test robust to simultaneous non-coherent sampling and amplitude clipping 准确的全谱测试鲁棒同时非相干采样和幅度裁剪

2013 IEEE International Test Conference (ITC) Pub Date : 2013-09-01 DOI: 10.1109/TEST.2013.6651920

Siva Sudani, Li Xu, Degang Chen

引用次数: 6

SmartScan - Hierarchical test compression for pin-limited low power designs SmartScan -用于引脚受限低功耗设计的分层测试压缩

2013 IEEE International Test Conference (ITC) Pub Date : 2013-09-01 DOI: 10.1109/TEST.2013.6651897

K. Chakravadhanula, V. Chickermane, D. Pearl, A. Garg, R. Khurana, Subhasish Mukherjee, P. Nagaraj

引用次数: 21

A pattern mining framework for inter-wafer abnormality analysis 晶圆间异常分析的模式挖掘框架

2013 IEEE International Test Conference (ITC) Pub Date : 2013-09-01 DOI: 10.1109/TEST.2013.6651890

N. Sumikawa, Li-C. Wang, M. Abadir

引用次数: 16

Test and debug strategy for TSMC CoWoS™ stacking process based heterogeneous 3D IC: A silicon case study 基于TSMC coos™堆叠工艺的异构3D集成电路测试与调试策略:以硅为例研究

2013 IEEE International Test Conference (ITC) Pub Date : 2013-09-01 DOI: 10.1109/TEST.2013.6651893

S. Goel, S. Adham, Min-Jer Wang, Ji-Jan Chen, Tze-Chiang Huang, Ashok Mehta, F. Lee, V. Chickermane, B. Keller, Thomas Valind, Subhasish Mukherjee, Navdeep Sood, Jeongho Cho, Hayden Lee, Jungi Choi, Sang-Duek Kim

{"title":"Test and debug strategy for TSMC CoWoS™ stacking process based heterogeneous 3D IC: A silicon case study","authors":"S. Goel, S. Adham, Min-Jer Wang, Ji-Jan Chen, Tze-Chiang Huang, Ashok Mehta, F. Lee, V. Chickermane, B. Keller, Thomas Valind, Subhasish Mukherjee, Navdeep Sood, Jeongho Cho, Hayden Lee, Jungi Choi, Sang-Duek Kim","doi":"10.1109/TEST.2013.6651893","DOIUrl":"https://doi.org/10.1109/TEST.2013.6651893","url":null,"abstract":"Recent advances in semiconductor process technology especially interconnects using Through Silicon Vias (TSVs) enable the heterogeneous system integration where dies are implemented in dedicated, optimized process technologies and stacked in a 3D form. TSMC has developed the CoWoS™ (Chip on Wafer on Substrate) process as a design paradigm to assemble silicon interposer-based 3D ICs. To reach quality requirements for volume production, several test challenges related to 3D ICs need to be addressed. This paper describes the test and debug strategy used in designing a CoWoS™ based stacked IC. The 3D design presented in the paper contains three heterogeneous dies (a logic, a DRAM, and a JEDEC Wide-I/O compliant DRAM) stacked on the top of a passive interposer. For passive interposer testing, a novel test methodology called Pretty-Good-Die (PGD) test is presented, while for inter-die test, a novel scalable multi-tower 3D DFT architecture is presented. Silicon results show that most of the test challenges can be solved efficiently if planned properly; and 3D ICs are reality and not a fiction anymore.","PeriodicalId":6379,"journal":{"name":"2013 IEEE International Test Conference (ITC)","volume":"70 1","pages":"1-10"},"PeriodicalIF":0.0,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76706790","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 32

Don't forget to lock your SIB: hiding instruments using P1687 不要忘记锁定你的SIB:隐藏仪器使用P1687

2013 IEEE International Test Conference (ITC) Pub Date : 2013-09-01 DOI: 10.1109/TEST.2013.6651903

Jennifer Dworak, A. Crouch, John C. Potter, Adam Zygmontowicz, Micah Thornton

引用次数: 73

Test time reduction with SATOM: Simultaneous AC-DC Test with Orthogonal Multi-excitations 用SATOM减少试验时间:正交多激励的交直流同时试验

2013 IEEE International Test Conference (ITC) Pub Date : 2013-09-01 DOI: 10.1109/TEST.2013.6651912

Degang Chen, Zhongjun Yu, Krunal Maniar, M. Nowrozi

引用次数: 1