SmartScan - Hierarchical test compression for pin-limited low power designs

Abstract

IP cores that are embedded in SoCs usually include embedded test compression hardware. When multiple cores are embedded in a SoC with limited tester-contacted pins, there is a need for a structured test-access mechanism (TAM) architecture that allows compressed test data stimuli and responses to be efficiently distributed to the embedded cores. This paper presents SmartScan, a TAM architecture that is based on time-domain multiplexing of compressed data. Results on industrial designs show that high quality compressed ATPG patterns can be efficiently re-applied in a very low-pin SoC test environment with very low overhead.