自适应测试——通过测试模式采样降低成本

2013 IEEE International Test Conference (ITC) Pub Date : 2013-09-01 DOI:10.1109/TEST.2013.6651891

M. Grady, Bradley Pepper, Joshua Patch, Mike Degregorio, P. Nigh

{"title":"自适应测试——通过测试模式采样降低成本","authors":"M. Grady, Bradley Pepper, Joshua Patch, Mike Degregorio, P. Nigh","doi":"10.1109/TEST.2013.6651891","DOIUrl":null,"url":null,"abstract":"In this paper, we will present two different applications of “test pattern sampling” for logic testing that have significantly improved test cost for Processors and SOCs/ASICs at IBM. The drivers and implementations for these two methods were completely different - one relying on real-time analysis/optimization applied at wafer test; the other based on off-line analysis with daily updates and real-time adjustments at Final Test.","PeriodicalId":6379,"journal":{"name":"2013 IEEE International Test Conference (ITC)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2013-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"13","resultStr":"{\"title\":\"Adaptive testing - Cost reduction through test pattern sampling\",\"authors\":\"M. Grady, Bradley Pepper, Joshua Patch, Mike Degregorio, P. Nigh\",\"doi\":\"10.1109/TEST.2013.6651891\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we will present two different applications of “test pattern sampling” for logic testing that have significantly improved test cost for Processors and SOCs/ASICs at IBM. The drivers and implementations for these two methods were completely different - one relying on real-time analysis/optimization applied at wafer test; the other based on off-line analysis with daily updates and real-time adjustments at Final Test.\",\"PeriodicalId\":6379,\"journal\":{\"name\":\"2013 IEEE International Test Conference (ITC)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"13\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 IEEE International Test Conference (ITC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/TEST.2013.6651891\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE International Test Conference (ITC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/TEST.2013.6651891","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 13

摘要

在本文中，我们将介绍用于逻辑测试的“测试模式采样”的两种不同应用，它们显著提高了IBM处理器和soc / asic的测试成本。这两种方法的驱动和实现完全不同——一种依赖于硅片测试中应用的实时分析/优化;另一种基于离线分析，每日更新和最终测试时的实时调整。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Adaptive testing - Cost reduction through test pattern sampling

In this paper, we will present two different applications of “test pattern sampling” for logic testing that have significantly improved test cost for Processors and SOCs/ASICs at IBM. The drivers and implementations for these two methods were completely different - one relying on real-time analysis/optimization applied at wafer test; the other based on off-line analysis with daily updates and real-time adjustments at Final Test.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2013 IEEE International Test Conference (ITC)

自引率

0.00%

发文量