2013 IEEE International Test Conference (ITC)最新文献_第2页

Application of under-approximation techniques to functional test generation targeting hard to detect stuck-at faults 欠逼近技术在难以检测到卡滞故障的功能测试生成中的应用

2013 IEEE International Test Conference (ITC) Pub Date : 2013-11-04 DOI: 10.1109/TEST.2013.6651915

M. Prabhu, J. Abraham

{"title":"Application of under-approximation techniques to functional test generation targeting hard to detect stuck-at faults","authors":"M. Prabhu, J. Abraham","doi":"10.1109/TEST.2013.6651915","DOIUrl":"https://doi.org/10.1109/TEST.2013.6651915","url":null,"abstract":"Running at-speed functional tests has shown to be a very effective method to detect faulty chips. In our previous paper we presented a methodology for generating functional tests aimed at hard to detect gate level faults in the control logic of a processor. In that methodology gate level tests were mapped to the register transfer level (RTL) and a faulty RTL model was built. The propagation constraints of the fault through the design were captured as linear temporal logic (LTL) properties. These constraints reduced the search space. Further, the constraints also allowed us to do structural reductions like cone of influence reduction and removal of irrelevant duplicated signals. Overall the constraints provided improved scaling. Not all the design behaviours are required to generate a test for a fault. In this paper we use this insight to scale our previous methodology further. Under-approximations are design abstractions that only capture a subset of the orignial design behaviors. The use of RTL for test generation affords us two types of under-approximations: bit-width reduction and operator approximation. Our experiments show that the use of these two under-approximations can achive 2× to 3× reduction in test generation time without compromising the fault coverage.","PeriodicalId":6379,"journal":{"name":"2013 IEEE International Test Conference (ITC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86290500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Counterfeit electronics: A rising threat in the semiconductor manufacturing industry 假冒电子产品:半导体制造行业日益严重的威胁

2013 IEEE International Test Conference (ITC) Pub Date : 2013-11-04 DOI: 10.1109/TEST.2013.6651880

K. Huang, J. Carulli, Y. Makris

引用次数: 44

Fault diagnosis of TSV-based interconnects in 3-D stacked designs 三维堆叠设计中基于tsv的互连故障诊断

2013 IEEE International Test Conference (ITC) Pub Date : 2013-11-04 DOI: 10.1109/TEST.2013.6651894

J. Rajski, J. Tyszer

引用次数: 15

True non-intrusive sensors for RF built-in test 真正的非侵入式传感器射频内置测试

2013 IEEE International Test Conference (ITC) Pub Date : 2013-11-04 DOI: 10.1109/TEST.2013.6651885

L. Abdallah, H. Stratigopoulos, S. Mir

引用次数: 10

On the generation of compact test sets 关于紧测试集的生成

2013 IEEE International Test Conference (ITC) Pub Date : 2013-11-04 DOI: 10.1109/TEST.2013.6651914

Amit Kumar, J. Rajski, S. Reddy, Chen Wang

引用次数: 6

Practical methods for extending ATE to 40 and 50Gbps 将ATE扩展到40和50Gbps的实用方法

2013 IEEE International Test Conference (ITC) Pub Date : 2013-11-04 DOI: 10.1109/TEST.2013.6651876

D. Keezer, C. Gray, Te-Hui Chen, A. Majid

引用次数: 2

Uncertainty-aware robust optimization of test-access architectures for 3D stacked ICs 三维堆叠集成电路测试存取架构的不确定性感知鲁棒优化

2013 IEEE International Test Conference (ITC) Pub Date : 2013-11-04 DOI: 10.1109/TEST.2013.6651905

Sergej Deutsch, K. Chakrabarty, E. Marinissen

{"title":"Uncertainty-aware robust optimization of test-access architectures for 3D stacked ICs","authors":"Sergej Deutsch, K. Chakrabarty, E. Marinissen","doi":"10.1109/TEST.2013.6651905","DOIUrl":"https://doi.org/10.1109/TEST.2013.6651905","url":null,"abstract":"3D integration using through-silicon vias offers many benefits, such as high bandwidth, low power, and small footprint. However, test complexity and test cost are major concerns for 3D-SICs. Recent work on the optimization of 3D test architectures to reduce test cost suffer from the drawback that they ignore potential uncertainties in input parameters; they consider only a single point in the input-parameter space. In realistic scenarios, the assumed values for parameters such as test power and pattern count of logic cores, which are used for optimizing the test architecture for a die, may differ from the actual values that are known only after the design stage. In a 3D setting, a die can be used in multiple stacks each with different properties. As a result, the originally designed test architecture might no longer be optimal, which leads to an undesirable increase in the test cost. We propose an optimization approach that takes uncertainties in input parameters into account and provides a solution that is efficient in the presence of input-parameter variations. We use integer linear programming (ILP) to formulate the robust test-architecture optimization problem, and the resulting ILP model serves as the basis for a heuristic solution that scales well for large designs. The proposed optimization framework is evaluated using the ITC'02 SoC benchmarks and we show that robust solutions are superior to single-point solutions in terms of average test time when there are uncertainties in the values of input parameters.","PeriodicalId":6379,"journal":{"name":"2013 IEEE International Test Conference (ITC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73291696","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

12Gbps SerDes Jitter Tolerance BIST in production loopback testing with enhanced spread spectrum clock generation circuit 12Gbps SerDes抖动容限BIST在生产环回测试与增强扩频时钟产生电路

2013 IEEE International Test Conference (ITC) Pub Date : 2013-11-04 DOI: 10.1109/TEST.2013.6651882

Y. Cai, Liming Fang, Ivan Chan, M. Olsen, Kevin Richter

引用次数: 4

Test data analytics — Exploring spatial and test-item correlations in production test data 测试数据分析-探索生产测试数据中的空间和测试项目相关性

2013 IEEE International Test Conference (ITC) Pub Date : 2013-11-04 DOI: 10.1109/TEST.2013.6651900

Chun-Kai Hsu, Fan Lin, K. Cheng, Wangyang Zhang, Xin Li, J. Carulli, K. Butler

{"title":"Test data analytics — Exploring spatial and test-item correlations in production test data","authors":"Chun-Kai Hsu, Fan Lin, K. Cheng, Wangyang Zhang, Xin Li, J. Carulli, K. Butler","doi":"10.1109/TEST.2013.6651900","DOIUrl":"https://doi.org/10.1109/TEST.2013.6651900","url":null,"abstract":"The discovery of patterns and correlations hidden in the test data could help reduce test time and cost. In this paper, we propose a methodology and supporting statistical regression tools that can exploit and utilize both spatial and inter-test-item correlations in the test data for test time and cost reduction. We first describe a statistical regression method, called group lasso, which can identify inter-test-item correlations from test data. After learning such correlations, some test items can be identified for removal from the test program without compromising test quality. An extended version of this method, weighted group lasso, allows taking into account the distinct test time/cost of each individual test item in the formulation as a weighted optimization problem. As a result, its solution would favor more costly test items for removal from the test program. We further integrate weighted group lasso with another statistical regression technique, virtual probe, which can learn spatial correlations of test data across a wafer. The integrated method could then utilize both spatial and inter-test-item correlations to maximize the number of test items whose values can be predicted without measurement. Experimental results of a high-volume industrial device show that utilizing both spatial and inter-test-item correlations can help reduce test time by up to 55%.","PeriodicalId":6379,"journal":{"name":"2013 IEEE International Test Conference (ITC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84023943","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 30

Towards data reliable crossbar-based memristive memories 迈向数据可靠的基于横条的记忆存储器

2013 IEEE International Test Conference (ITC) Pub Date : 2013-11-04 DOI: 10.1109/TEST.2013.6651928

A. Ghofrani, M. Lastras-Montaño, K. Cheng

引用次数: 31