Application of under-approximation techniques to functional test generation targeting hard to detect stuck-at faults

Abstract

Running at-speed functional tests has shown to be a very effective method to detect faulty chips. In our previous paper we presented a methodology for generating functional tests aimed at hard to detect gate level faults in the control logic of a processor. In that methodology gate level tests were mapped to the register transfer level (RTL) and a faulty RTL model was built. The propagation constraints of the fault through the design were captured as linear temporal logic (LTL) properties. These constraints reduced the search space. Further, the constraints also allowed us to do structural reductions like cone of influence reduction and removal of irrelevant duplicated signals. Overall the constraints provided improved scaling. Not all the design behaviours are required to generate a test for a fault. In this paper we use this insight to scale our previous methodology further. Under-approximations are design abstractions that only capture a subset of the orignial design behaviors. The use of RTL for test generation affords us two types of under-approximations: bit-width reduction and operator approximation. Our experiments show that the use of these two under-approximations can achive 2× to 3× reduction in test generation time without compromising the fault coverage.