The implementation and application of a protocol aware architecture

Abstract

System On a Chip and other highly integrated mixed signal devices have exploded in design and function complexity. New device designs exhibit non-determinism in timing, phase and data; functional blocks without a coherent shared time base; and the integration of many differing protocols and external busses. Traditional semiconductor ATE addresses these challenges with stored stimulus and response vectors and pre-planned timing, greatly increasing the difficulty of debug, lowering development productivity and reducing test coverage. The challenge is further extended by multi-site and concurrent test. Recent ideas in the development of protocol aware test methods and architectures promise to meet these challenges and introduce a new paradigm for test development. This paper will present an implementation of these ideas in a new digital channel architecture and demonstrate their application in a complete mixed signal SOC semiconductor ATE design.