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2012 Symposium on VLSI Circuits (VLSIC)最新文献

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A 28nm high-k metal-gate SRAM with Asynchronous Cross-Couple Read Assist (AC2RA) circuitry achieving 3x reduction on speed variation for single ended arrays 28nm高k金属门SRAM，具有异步交叉偶读辅助(AC2RA)电路，可将单端阵列的速度变化降低3倍
2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI: 10.1109/VLSIC.2012.6243791
Robin Lee, Jung-Ping Yang, Chia-En Huang, Chih-Chieh Chiu, Wei-Shuo Kao, Hong-Chen Cheng, H. Liao, Jonathan Chang
{"title":"A 28nm high-k metal-gate SRAM with Asynchronous Cross-Couple Read Assist (AC2RA) circuitry achieving 3x reduction on speed variation for single ended arrays","authors":"Robin Lee, Jung-Ping Yang, Chia-En Huang, Chih-Chieh Chiu, Wei-Shuo Kao, Hong-Chen Cheng, H. Liao, Jonathan Chang","doi":"10.1109/VLSIC.2012.6243791","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243791","url":null,"abstract":"Asynchronous Cross-Couple Read Assist (AC2RA) circuitry scheme was invented for single-ended sensing to minimize speed variation in 28nm HKMG process. It improves SRAM array speed variation by 63.3% which is adequate to cover 6σ variation. Access time is also boosted by faster sensing.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"71 1","pages":"64-65"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87699827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 3.14 um2 4T-2MTJ-cell fully parallel TCAM based on nonvolatile logic-in-memory architecture 基于非易失性内存逻辑架构的3.14 um2 4t - 2mtj单元全并行TCAM
2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI: 10.1109/VLSIC.2012.6243781
S. Matsunaga, S. Miura, H. Honjo, K. Kinoshita, S. Ikeda, T. Endoh, H. Ohno, T. Hanyu
{"title":"A 3.14 um2 4T-2MTJ-cell fully parallel TCAM based on nonvolatile logic-in-memory architecture","authors":"S. Matsunaga, S. Miura, H. Honjo, K. Kinoshita, S. Ikeda, T. Endoh, H. Ohno, T. Hanyu","doi":"10.1109/VLSIC.2012.6243781","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243781","url":null,"abstract":"A four-MOS-transistor/two-MTJ-device (4T-2MTJ) cell circuit is proposed and fabricated for a standby-power-free and a high-density fully parallel nonvolatile TCAM. By optimally merging a nonvolatile storage function and a comparison logic function into a TCAM cell circuit with a nonvolatile logic-in-memory structure, the transistor counts required in the cell circuit become minimized. As a result, the cell size becomes 3.14um2 under a 90-nm CMOS and a 100-nm MTJ technologies, which achieves 60% and 86% of area reduction in comparison with that of a 12T-SRAM-based and a 16T-SRAM-based TCAM cell circuit, respectively.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"60 1","pages":"44-45"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91346126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 83
Isolated Preset Architecture for a 32nm SOI embedded DRAM macro 32纳米SOI嵌入式DRAM宏的隔离预置架构
2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI: 10.1109/VLSIC.2012.6243814
J. Barth, D. Plass, Adis Vehabovic, R. Joshi, R. Kanj, S. Burns, T. Weaver
{"title":"Isolated Preset Architecture for a 32nm SOI embedded DRAM macro","authors":"J. Barth, D. Plass, Adis Vehabovic, R. Joshi, R. Kanj, S. Burns, T. Weaver","doi":"10.1109/VLSIC.2012.6243814","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243814","url":null,"abstract":"The Isolated Preset Architecture (IPA) improves retention characteristics by implementing a weak read `1' Isolation scheme, allowing a lower stored `1' level to be sensed. The architecture also reduces sub-array area by 15% and bit-line activation power by 2× compared to previous design, without impacting performance. The architecture was implemented in IBM's 32nm High-K/Metal SOI embedded DRAM technology. Hardware results confirm 1.8ns random cycle and 2× improved retention characteristic with optimized Analog reference tuning.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"21 1","pages":"110-111"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81895510","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 2.98nW bandgap voltage reference using a self-tuning low leakage sample and hold 一个2.98nW带隙基准电压，采用自调谐低漏采样和保持器
2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI: 10.1109/VLSIC.2012.6243859
Yen-Po Chen, Matthew R. Fojtik, D. Blaauw, D. Sylvester
{"title":"A 2.98nW bandgap voltage reference using a self-tuning low leakage sample and hold","authors":"Yen-Po Chen, Matthew R. Fojtik, D. Blaauw, D. Sylvester","doi":"10.1109/VLSIC.2012.6243859","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243859","url":null,"abstract":"A novel low power bandgap voltage reference using a sample and hold circuit with self-calibrating duty cycle and leakage compensation is presented. Measurements of 0.18μm CMOS test chips show a temperature coefficient of 24.7ppm/°C and power consumption of 2.98nW, marking a 251× power reduction over the previous lowest power bandgap reference.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"19 1","pages":"200-201"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89417548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 31
A 25-Gb/s 5-mWCMOS CDR/deserializer 25gb /s 5-mWCMOS CDR/反序列化器
2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI: 10.1109/VLSIC.2012.6243828
Jun Won Jung, B. Razavi
{"title":"A 25-Gb/s 5-mWCMOS CDR/deserializer","authors":"Jun Won Jung, B. Razavi","doi":"10.1109/VLSIC.2012.6243828","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243828","url":null,"abstract":"A half-rate clock and data recovery circuit and a deserializer employ charge-steering logic to reduce the power consumption. Realized in 65-nm technology, the overall circuit draws 5 mW from a 1-V supply, producing a clock with an rms jitter of 1.5 ps and a jitter tolerance of 0.5 UIpp at 5 MHz.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"5 1","pages":"138-139"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75644240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Voltage droop reduction using throttling controlled by timing margin feedback 利用时序余量反馈控制的节流减小电压降
2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI: 10.1109/VLSIC.2012.6243807
M. Floyd, A. Drake, R. Berry, H. Chase, Richard L. Willaman, Jarom Pena
{"title":"Voltage droop reduction using throttling controlled by timing margin feedback","authors":"M. Floyd, A. Drake, R. Berry, H. Chase, Richard L. Willaman, Jarom Pena","doi":"10.1109/VLSIC.2012.6243807","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243807","url":null,"abstract":"An active processor throttling control loop using critical path timing measurements is enabled in the shipping POWER7™ based P775 supercomputer to prevent voltage droop induced failures. As a result, worst-case workload-induced voltage droop events are reduced by more than 50% compared to the system operating without the control loop. The reduction in operating voltage afforded by this technique translates to significant yield improvement, reduced failure rates, and improved power efficiency.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"25 1","pages":"96-97"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75533644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A standard cell compatible bidirectional repeater with thyristor assist 标准单元兼容双向中继器与晶闸管辅助
2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI: 10.1109/VLSIC.2012.6243846
Sudhir K. Satpathy, D. Sylvester, D. Blaauw
{"title":"A standard cell compatible bidirectional repeater with thyristor assist","authors":"Sudhir K. Satpathy, D. Sylvester, D. Blaauw","doi":"10.1109/VLSIC.2012.6243846","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243846","url":null,"abstract":"A thyristor-assisted standard cell compatible self-timed bidirectional repeater with no configuration overhead enables 8mm interconnects to achieve 37% higher speed at 20% lower energy over conventional repeaters in 65nm CMOS at 1.0V. Bidirectional operation without the need for configuration logic removes the need for clocking, yielding up to 14× higher energy efficiency at low data switching activity.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"64 1","pages":"174-175"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73832449","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 0.45-V input on-chip gate boosted (OGB) buck converter in 40-nm CMOS with more than 90% efficiency in load range from 2µW to 50µW 一种0.45 v输入片上栅极升压(OGB) 40纳米CMOS降压变换器，在2µW至50µW负载范围内效率超过90%
2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI: 10.1109/VLSIC.2012.6243856
Xin Zhang, Po-Hung Chen, Y. Ryu, K. Ishida, Yasuyuki Okuma, Kazunori Watanabe, T. Sakurai, M. Takamiya
{"title":"A 0.45-V input on-chip gate boosted (OGB) buck converter in 40-nm CMOS with more than 90% efficiency in load range from 2µW to 50µW","authors":"Xin Zhang, Po-Hung Chen, Y. Ryu, K. Ishida, Yasuyuki Okuma, Kazunori Watanabe, T. Sakurai, M. Takamiya","doi":"10.1109/VLSIC.2012.6243856","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243856","url":null,"abstract":"A 0.45-V input, 0.4-V output on-chip gate boosted (OGB) buck converter with clock gated digital PWM controller in 40-nm CMOS achieved the highest efficiency to date with the output power less than 40μW. A linear delay trimming by a logarithmic stress voltage (LSV) scheme to compensate for the die-to-die delay variations of a delay line in the PWM controller with good controllability is also proposed.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"44 1","pages":"194-195"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80151595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
A fully electrical startup batteryless boost converter with 50mV input voltage for thermoelectric energy harvesting 一种全电启动无电池升压转换器，输入电压为50mV，用于热电能量收集
2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI: 10.1109/VLSIC.2012.6243857
Hao-Yen Tang, Po-Shuan Weng, P. Ku, Liang-Hung Lu
{"title":"A fully electrical startup batteryless boost converter with 50mV input voltage for thermoelectric energy harvesting","authors":"Hao-Yen Tang, Po-Shuan Weng, P. Ku, Liang-Hung Lu","doi":"10.1109/VLSIC.2012.6243857","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243857","url":null,"abstract":"A fully electrical startup boost converter is presented in this paper. With a three-stage stepping-up architecture, the proposed circuit is capable of performing thermoelectric energy harvesting at an input voltage as low as 50 mV. Due to the zero-current-switching (ZCS) operation of the boost converter and automatic shutdown of the low-voltage starter and the auxiliary converter, conversion efficiency up to 73% is demonstrated. The boost converter does not require bulky transformers or mechanical switches for kick-start, making it very attractive for body area sensor network applications.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"18 1","pages":"196-197"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87173553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
A 2.8GHz 128-entry × 152b 3-read/2-write multi-precision floating-point register file and shuffler in 32nm CMOS 基于32nm CMOS的2.8GHz 128入口× 152b 3读2写多精度浮点寄存器文件和shuffle
2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI: 10.1109/VLSIC.2012.6243818
S. Hsu, A. Agarwal, M. Anders, Himanshu Kaul, S. Mathew, F. Sheikh, R. Krishnamurthy, S. Borkar
{"title":"A 2.8GHz 128-entry × 152b 3-read/2-write multi-precision floating-point register file and shuffler in 32nm CMOS","authors":"S. Hsu, A. Agarwal, M. Anders, Himanshu Kaul, S. Mathew, F. Sheikh, R. Krishnamurthy, S. Borkar","doi":"10.1109/VLSIC.2012.6243818","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243818","url":null,"abstract":"A 128-entry × 152b 3-read/2-write ported multi-precision floating-point register file/shuffler with measured 2.8GHz operation is fabricated in 1.05V, 32nm CMOS. Single-precision (24b-mantissa), 2-way 12b or 4-way 6b reduced mantissa precision modes, certainty tracking bits, mode-dependent gating, area-efficient windowing using 1R/1W cells, and ultra-low-voltage read/write circuits enable 350mV-1.2V wide dynamic voltage range with measured peak energy-efficiency of 751GOPS/W at 400mV, 4-way 6b-mode (22.3× higher than 1.05V single-precision mode) and 19% area reduction over single-precision 3R/2W implementations.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"278 1","pages":"118-119"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83428208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
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