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A −70dBm-sensitivity 522Mbps 0.19nJ/bit-TX 0.43nJ/bit-RX transceiver for TransferJet™ SoC in 65nm CMOS - 70dbm灵敏度522Mbps 0.19nJ/bit-TX 0.43nJ/bit-RX收发器，用于TransferJet™SoC, 65nm CMOS
2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI: 10.1109/VLSIC.2012.6243796
D. Miyashita, K. Agawa, H. Kajihara, K. Sami, Masaomi Iwanaga, Y. Ogasawara, Tomohiko Ito, Daisuke Kurose, N. Koide, Toru Hashimoto, H. Sakurai, T. Yamaji, T. Kurihara, Kazumi Sato, I. Seto, H. Yoshida, R. Fujimoto, Y. Unekawa
{"title":"A −70dBm-sensitivity 522Mbps 0.19nJ/bit-TX 0.43nJ/bit-RX transceiver for TransferJet™ SoC in 65nm CMOS","authors":"D. Miyashita, K. Agawa, H. Kajihara, K. Sami, Masaomi Iwanaga, Y. Ogasawara, Tomohiko Ito, Daisuke Kurose, N. Koide, Toru Hashimoto, H. Sakurai, T. Yamaji, T. Kurihara, Kazumi Sato, I. Seto, H. Yoshida, R. Fujimoto, Y. Unekawa","doi":"10.1109/VLSIC.2012.6243796","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243796","url":null,"abstract":"TransferJet™ is an emerging high-speed close-proximity wireless communication standard, which enables a data transfer of up to 522Mbps within a few centimeters range. We have developed a fully integrated TransferJet SoC with a 4.48-GHz operating frequency and a 560-MHz bandwidth (BW) using 65nm CMOS technology. Baseband filtering techniques for both a transmitter (TX) and a receiver (RX) are proposed to obtain a sensitivity of -70dBm with low power consumption. The SoC achieves an energy per bit of 0.19nJ/bit and 0.43nJ/bit for the TX and the RX, respectively, We have also built the world's smallest module prototype using the SoC, which is suitable for small mobile devices.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"14 1","pages":"74-75"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73318068","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
A 13.8pJ/Access/Mbit SRAM with charge collector circuits for effective use of non-selected bit line charges 带电荷收集器电路的13.8pJ/Access/Mbit SRAM，可有效地利用非选择的位线电荷
2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI: 10.1109/VLSIC.2012.6243789
S. Moriwaki, Yasuhiro Yamamoto, A. Kawasumi, Toshikazu Suzuki, S. Miyano, T. Sakurai, H. Shinohara
{"title":"A 13.8pJ/Access/Mbit SRAM with charge collector circuits for effective use of non-selected bit line charges","authors":"S. Moriwaki, Yasuhiro Yamamoto, A. Kawasumi, Toshikazu Suzuki, S. Miyano, T. Sakurai, H. Shinohara","doi":"10.1109/VLSIC.2012.6243789","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243789","url":null,"abstract":"1Mb SRAM with charge collector circuits for effective use of non-selected bit line charges has been fabricated in 40nm technology. These circuits reduce two major wasted power sources of the low voltage SRAM: excess bit line swing due to random variation and bit line swing of non-selected columns. The lowest power consumption of 13.8pJ/Access/Mbit in the previous works has been achieved.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"46 6 1","pages":"60-61"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89582445","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A 3.14 um2 4T-2MTJ-cell fully parallel TCAM based on nonvolatile logic-in-memory architecture 基于非易失性内存逻辑架构的3.14 um2 4t - 2mtj单元全并行TCAM
2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI: 10.1109/VLSIC.2012.6243781
S. Matsunaga, S. Miura, H. Honjo, K. Kinoshita, S. Ikeda, T. Endoh, H. Ohno, T. Hanyu
{"title":"A 3.14 um2 4T-2MTJ-cell fully parallel TCAM based on nonvolatile logic-in-memory architecture","authors":"S. Matsunaga, S. Miura, H. Honjo, K. Kinoshita, S. Ikeda, T. Endoh, H. Ohno, T. Hanyu","doi":"10.1109/VLSIC.2012.6243781","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243781","url":null,"abstract":"A four-MOS-transistor/two-MTJ-device (4T-2MTJ) cell circuit is proposed and fabricated for a standby-power-free and a high-density fully parallel nonvolatile TCAM. By optimally merging a nonvolatile storage function and a comparison logic function into a TCAM cell circuit with a nonvolatile logic-in-memory structure, the transistor counts required in the cell circuit become minimized. As a result, the cell size becomes 3.14um2 under a 90-nm CMOS and a 100-nm MTJ technologies, which achieves 60% and 86% of area reduction in comparison with that of a 12T-SRAM-based and a 16T-SRAM-based TCAM cell circuit, respectively.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"60 1","pages":"44-45"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91346126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 83
An integral path self-calibration scheme for a 20.1–26.7GHz dual-loop PLL in 32nm SOI CMOS 基于32nm SOI CMOS的20.1-26.7GHz双环锁相环积分路径自校准方案
2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI: 10.1109/VLSIC.2012.6243847
M. Ferriss, J. Plouchart, A. Natarajan, A. Rylyakov, B. Parker, A. Babakhani, Soner Yaldiz, B. Sadhu, A. Valdes-Garcia, J. Tierno, D. Friedman
{"title":"An integral path self-calibration scheme for a 20.1–26.7GHz dual-loop PLL in 32nm SOI CMOS","authors":"M. Ferriss, J. Plouchart, A. Natarajan, A. Rylyakov, B. Parker, A. Babakhani, Soner Yaldiz, B. Sadhu, A. Valdes-Garcia, J. Tierno, D. Friedman","doi":"10.1109/VLSIC.2012.6243847","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243847","url":null,"abstract":"A bandwidth self-calibration scheme is introduced as part of a 20.1GHz to 26.7GHz, low noise PLL in 32nm CMOS SOI. A dual-loop architecture in combination with an integral path measurement and correction scheme desensitizes the loop transfer function to the VCO's small signal gain variations. The spread of gain peaking is reduced by self-calibration from 2.4dB to 1dB, when measured at 70 sites on a 300mm wafer. The PLL has a measured phase noise @10MHz offset of -126.5dBc/Hz at 20.1GHz.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"54 1","pages":"176-177"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84918429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A 25-Gb/s 5-mWCMOS CDR/deserializer 25gb /s 5-mWCMOS CDR/反序列化器
2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI: 10.1109/VLSIC.2012.6243828
Jun Won Jung, B. Razavi
{"title":"A 25-Gb/s 5-mWCMOS CDR/deserializer","authors":"Jun Won Jung, B. Razavi","doi":"10.1109/VLSIC.2012.6243828","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243828","url":null,"abstract":"A half-rate clock and data recovery circuit and a deserializer employ charge-steering logic to reduce the power consumption. Realized in 65-nm technology, the overall circuit draws 5 mW from a 1-V supply, producing a clock with an rms jitter of 1.5 ps and a jitter tolerance of 0.5 UIpp at 5 MHz.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"5 1","pages":"138-139"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75644240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Voltage droop reduction using throttling controlled by timing margin feedback 利用时序余量反馈控制的节流减小电压降
2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI: 10.1109/VLSIC.2012.6243807
M. Floyd, A. Drake, R. Berry, H. Chase, Richard L. Willaman, Jarom Pena
{"title":"Voltage droop reduction using throttling controlled by timing margin feedback","authors":"M. Floyd, A. Drake, R. Berry, H. Chase, Richard L. Willaman, Jarom Pena","doi":"10.1109/VLSIC.2012.6243807","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243807","url":null,"abstract":"An active processor throttling control loop using critical path timing measurements is enabled in the shipping POWER7™ based P775 supercomputer to prevent voltage droop induced failures. As a result, worst-case workload-induced voltage droop events are reduced by more than 50% compared to the system operating without the control loop. The reduction in operating voltage afforded by this technique translates to significant yield improvement, reduced failure rates, and improved power efficiency.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"25 1","pages":"96-97"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75533644","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Circuit techniques to overcome Class-D audio amplifier limitations in mobile devices 克服移动设备中d类音频放大器限制的电路技术
2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI: 10.1109/VLSIC.2012.6243768
Xicheng Jiang, Jungwoo Song, Minsheng Wang, Jianlong Chen, S. Arunachalam, T. Brooks
{"title":"Circuit techniques to overcome Class-D audio amplifier limitations in mobile devices","authors":"Xicheng Jiang, Jungwoo Song, Minsheng Wang, Jianlong Chen, S. Arunachalam, T. Brooks","doi":"10.1109/VLSIC.2012.6243768","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243768","url":null,"abstract":"Circuit techniques to overcome practical noise, reliability, and EMI limitations are reported. An auxiliary loop with ramping circuits suppresses pop-and-click noise to 1 mV for an amplifier with 4V achievable output voltage. Switching edge rate control enables the system to meet the EN55022 Class-B standard with a 15 dB margin. An enhanced scheme detects short-circuit conditions without relying on over-limit current events.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"34 1","pages":"18-19"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79075095","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A fully electrical startup batteryless boost converter with 50mV input voltage for thermoelectric energy harvesting 一种全电启动无电池升压转换器，输入电压为50mV，用于热电能量收集
2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI: 10.1109/VLSIC.2012.6243857
Hao-Yen Tang, Po-Shuan Weng, P. Ku, Liang-Hung Lu
{"title":"A fully electrical startup batteryless boost converter with 50mV input voltage for thermoelectric energy harvesting","authors":"Hao-Yen Tang, Po-Shuan Weng, P. Ku, Liang-Hung Lu","doi":"10.1109/VLSIC.2012.6243857","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243857","url":null,"abstract":"A fully electrical startup boost converter is presented in this paper. With a three-stage stepping-up architecture, the proposed circuit is capable of performing thermoelectric energy harvesting at an input voltage as low as 50 mV. Due to the zero-current-switching (ZCS) operation of the boost converter and automatic shutdown of the low-voltage starter and the auxiliary converter, conversion efficiency up to 73% is demonstrated. The boost converter does not require bulky transformers or mechanical switches for kick-start, making it very attractive for body area sensor network applications.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"18 1","pages":"196-197"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87173553","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
High-resolution sensing sheet for structural-health monitoring via scalable interfacing of flexible electronics with high-performance ICs 通过柔性电子器件与高性能集成电路的可扩展接口，用于结构健康监测的高分辨率传感片
2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI: 10.1109/VLSIC.2012.6243819
Yingzhe Hu, W. Rieutort-Louis, J. Sanz-Robinson, K. Song, J. Sturm, S. Wagner, N. Verma
{"title":"High-resolution sensing sheet for structural-health monitoring via scalable interfacing of flexible electronics with high-performance ICs","authors":"Yingzhe Hu, W. Rieutort-Louis, J. Sanz-Robinson, K. Song, J. Sturm, S. Wagner, N. Verma","doi":"10.1109/VLSIC.2012.6243819","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243819","url":null,"abstract":"Early-stage damage detection for buildings and bridges requires continuously sensing and assessing strain over large surfaces, yet with centimeter-scale resolution. To achieve this, we present a sensing sheet that combines high-performance ICs with flexible electronics, allowing bonding to such surfaces. The flexible electronics integrates thin-film strain gauges and amorphous-silicon control circuits, patterned on a polyimide sheet that can potentially span large areas. Non-contact links couple digital and analog signals to the ICs, allowing many ICs to be introduced via low-cost sheet lamination for energy-efficient readout and computation over a large number of sensors. Communication between distributed ICs is achieved by transceivers that exploit low-loss interconnects patterned on the polyimide sheet; the transceivers self-calibrate to the interconnect impedance to maximize transmit SNR. The system achieves multi-channel strain readout with sensitivity of 18μStrainRMS at an energy per measurement of 270nJ, while the communication energy is 12.8pJ/3.3pJ per bit (Tx/Rx) over 7.5m.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"93 1","pages":"120-121"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76276232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A sub-1V 3.9µW bandgap reference with a 3σ inaccuracy of ±0.34% from −50°C to +150°C using piecewise-linear-current curvature compensation 采用分段线性电流曲率补偿的sub-1V 3.9µW带隙基准，在−50°C至+150°C范围内的3σ误差为±0.34%
2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI: 10.1109/VLSIC.2012.6243770
S. Sano, Yasuhiko Takahashi, M. Horiguchi, M. Ota
{"title":"A sub-1V 3.9µW bandgap reference with a 3σ inaccuracy of ±0.34% from −50°C to +150°C using piecewise-linear-current curvature compensation","authors":"S. Sano, Yasuhiko Takahashi, M. Horiguchi, M. Ota","doi":"10.1109/VLSIC.2012.6243770","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243770","url":null,"abstract":"A sub-1V 3.9μW bandgap reference (BGR) with small voltage variation of ±0.34% and low temperature drift (1mV) over a wide temperature range (-50°C ~ +150°C) and a wide voltage range (+0.9 V ~ +5.5V) by using a low power current mode BGR core and a piecewise-linear curvature compensation system. The BGR occupies 0.1mm<sup>2</sup> in 0.13μm CMOS technology with triple well structure.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"1 1","pages":"22-23"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85542030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
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