S. Hsu, A. Agarwal, M. Anders, Himanshu Kaul, S. Mathew, F. Sheikh, R. Krishnamurthy, S. Borkar
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A 2.8GHz 128-entry × 152b 3-read/2-write multi-precision floating-point register file and shuffler in 32nm CMOS
A 128-entry × 152b 3-read/2-write ported multi-precision floating-point register file/shuffler with measured 2.8GHz operation is fabricated in 1.05V, 32nm CMOS. Single-precision (24b-mantissa), 2-way 12b or 4-way 6b reduced mantissa precision modes, certainty tracking bits, mode-dependent gating, area-efficient windowing using 1R/1W cells, and ultra-low-voltage read/write circuits enable 350mV-1.2V wide dynamic voltage range with measured peak energy-efficiency of 751GOPS/W at 400mV, 4-way 6b-mode (22.3× higher than 1.05V single-precision mode) and 19% area reduction over single-precision 3R/2W implementations.
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