32纳米SOI嵌入式DRAM宏的隔离预置架构

2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI:10.1109/VLSIC.2012.6243814

J. Barth, D. Plass, Adis Vehabovic, R. Joshi, R. Kanj, S. Burns, T. Weaver

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引用次数: 0

摘要

隔离预置架构(IPA)通过实现弱读“1”隔离方案来改善保留特性，允许感知较低的存储“1”级别。与之前的设计相比，该架构还减少了15%的子阵列面积和2倍的位线激活功率，而不会影响性能。该架构采用IBM的32nm High-K/Metal SOI嵌入式DRAM技术实现。硬件结果证实了1.8ns随机周期和2倍改进的保留特性与优化的模拟参考调谐。

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Isolated Preset Architecture for a 32nm SOI embedded DRAM macro

The Isolated Preset Architecture (IPA) improves retention characteristics by implementing a weak read `1' Isolation scheme, allowing a lower stored `1' level to be sensed. The architecture also reduces sub-array area by 15% and bit-line activation power by 2× compared to previous design, without impacting performance. The architecture was implemented in IBM's 32nm High-K/Metal SOI embedded DRAM technology. Hardware results confirm 1.8ns random cycle and 2× improved retention characteristic with optimized Analog reference tuning.

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2012 Symposium on VLSI Circuits (VLSIC)

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