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2012 Symposium on VLSI Circuits (VLSIC)最新文献

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A 22nm dynamically adaptive clock distribution for voltage droop tolerance 一种22nm动态自适应时钟分布，用于电压下垂公差
2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI: 10.1109/VLSIC.2012.6243806
K. Bowman, Carlos Tokunaga, T. Karnik, V. De, J. Tschanz
{"title":"A 22nm dynamically adaptive clock distribution for voltage droop tolerance","authors":"K. Bowman, Carlos Tokunaga, T. Karnik, V. De, J. Tschanz","doi":"10.1109/VLSIC.2012.6243806","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243806","url":null,"abstract":"A 22nm all-digital dynamically adaptive clock distribution mitigates the impact of high-frequency supply voltage (VCC) droops on microprocessor performance and energy efficiency. Silicon measurements demonstrate simultaneous throughput gains and energy reductions ranging from 14% and 3% at 1.0V to 31% and 15% at 0.6V, respectively, for a 10% VCC droop.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"140 1","pages":"94-95"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80866890","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
A new 3-bit programming algorithm using SLC-to-TLC migration for 8MB/s high performance TLC NAND flash memory 针对8MB/s高性能TLC NAND闪存，提出一种基于slc到TLC迁移的3位新编程算法
2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI: 10.1109/VLSIC.2012.6243825
Seung-Hwan Shin, Dong-Kyo Shim, Jaeyong Jeong, O. Kwon, Sangyong Yoon, Myung-Hoon Choi, Tae-Young Kim, H. Park, Hyun-Jun Yoon, Youngsun Song, Yoon-Hee Choi, Sang-Won Shim, Yang-Lo Ahn, Ki-Tae Park, Jin-Man Han, K. Kyung, Young-Hyun Jun
{"title":"A new 3-bit programming algorithm using SLC-to-TLC migration for 8MB/s high performance TLC NAND flash memory","authors":"Seung-Hwan Shin, Dong-Kyo Shim, Jaeyong Jeong, O. Kwon, Sangyong Yoon, Myung-Hoon Choi, Tae-Young Kim, H. Park, Hyun-Jun Yoon, Youngsun Song, Yoon-Hee Choi, Sang-Won Shim, Yang-Lo Ahn, Ki-Tae Park, Jin-Man Han, K. Kyung, Young-Hyun Jun","doi":"10.1109/VLSIC.2012.6243825","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243825","url":null,"abstract":"We have developed a new 3-bit programming algorithm of high performance TLC(Triple-level-cell, 3-bit/cell) NAND flash memories for 20nm node and beyond. By using the proposed 3-bit algorithm based on reprogramming with SLC-to-TLC migration, performance and BER is improved by 50% and 68%, respectively, compared to conventional method. The proposed algorithm is successfully implemented in 21nm 64Gb TLC NAND flash product that provides 8MB/s write and 400MB/s read throughputs.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"43 1","pages":"132-133"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90497790","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 40
1Gsearch/sec Ternary Content Addressable Memory compiler with silicon-aware Early-Predict Late-Correct single-ended sensing 具有硅感知的早预测晚正确单端传感的1Gsearch/sec三元内容可寻址内存编译器
2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI: 10.1109/VLSIC.2012.6243817
I. Arsovski, Travis Hebig, Daniel Dobson, R. Wistort
{"title":"1Gsearch/sec Ternary Content Addressable Memory compiler with silicon-aware Early-Predict Late-Correct single-ended sensing","authors":"I. Arsovski, Travis Hebig, Daniel Dobson, R. Wistort","doi":"10.1109/VLSIC.2012.6243817","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243817","url":null,"abstract":"A Ternary Content Addressable Memory (TCAM) uses a two phase search operation where early prediction on its pre-search results prematurely activates the subsequent main-search operation, which is later interrupted only if the final pre-search results contradict the early prediction. This early main-search activation improves performance by 30%, while the low-probability of a late-correct has a negligible power impact. This Early Predict Late Correct (EPLC) sensing enables a high-performance TCAM compiler implemented in 32nm High-K Metal Gate SOI process to achieve 1Gsearch/sec throughput on a 2048×640bit TCAM instance while consuming only 0.76W. Embedded Deep-Trench (DT) capacitance for power supply noise mitigation adds 5% overhead for a total TCAM area of 1.56mm2.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"144 1","pages":"116-117"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89031814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A clock jitter reduction circuit using gated phase blending between self-delayed clock edges 一种在自延迟时钟边缘之间使用门控相位混合的时钟抖动减小电路
2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI: 10.1109/VLSIC.2012.6243830
K. Niitsu, Naohiro Harigai, D. Hirabayashi, D. Oki, Masato Sakurai, O. Kobayashi, Takahiro J. Yamaguchi, Haruo Kobayashi
{"title":"A clock jitter reduction circuit using gated phase blending between self-delayed clock edges","authors":"K. Niitsu, Naohiro Harigai, D. Hirabayashi, D. Oki, Masato Sakurai, O. Kobayashi, Takahiro J. Yamaguchi, Haruo Kobayashi","doi":"10.1109/VLSIC.2012.6243830","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243830","url":null,"abstract":"A clock jitter reduction circuit is presented that exploits the phase blending technique between the uncorrelated clock edges that are self-delayed by multiples of the clock cycle, nT. By blending uncorrelated clock edges, the output clock edges approach the ideal timing and, thus, timing jitter can be reduced by a factor of √2 per stage. There are three technical challenges to realize this: 1) generating uncorrelated clock edges, 2) phase averaging with small time offset from the ideal center position, and 3) minimizing the error in nT-delay being deviated from ideal nT. The proposed circuit overcomes each of these by exploiting an nT-delay, gated phase blending, and self-calibrated nT-delay elements, respectively. Measurement results with a 180-nm CMOS prototype chip demonstrated an approximately fourfold reduction in timing jitter from 30.2 ps to 8.8 ps in 500-MHz clock by cascading the proposed circuit with four-stages.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"99 1","pages":"142-143"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90008775","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
135 GHz 98 mW 10 Gbps ASK transmitter and receiver chipset in 40 nm CMOS 135 GHz 98 mW 10 Gbps ASK发射器和接收器芯片组在40纳米CMOS
2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI: 10.1109/VLSIC.2012.6243784
N. Ono, M. Motoyoshi, K. Takano, K. Katayama, R. Fujimoto, M. Fujishima
{"title":"135 GHz 98 mW 10 Gbps ASK transmitter and receiver chipset in 40 nm CMOS","authors":"N. Ono, M. Motoyoshi, K. Takano, K. Katayama, R. Fujimoto, M. Fujishima","doi":"10.1109/VLSIC.2012.6243784","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243784","url":null,"abstract":"An ASK transmitter and receiver chipset using 40 nm CMOS technology for wireless communication systems is described, in which a maximum data rate of 10 Gbps and power consumption of 98.4 mW are obtained with a carrier frequency of 135 GHz. A simple circuit and a modulation method to reduce power consumption are selected for the chipsets. To realize multi-gigabit wireless communication, the receiver is designed with consideration of the group delay optimization.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"23 1","pages":"50-51"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79419949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 31
A shorted global clock design for multi-GHz 3D stacked chips 多ghz 3D堆叠芯片的短路全局时钟设计
2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI: 10.1109/VLSIC.2012.6243844
L. Pang, P. Restle, M. Wordeman, J. Silberman, R. Franch, G. Maier
{"title":"A shorted global clock design for multi-GHz 3D stacked chips","authors":"L. Pang, P. Restle, M. Wordeman, J. Silberman, R. Franch, G. Maier","doi":"10.1109/VLSIC.2012.6243844","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243844","url":null,"abstract":"A global clock distribution technique for 3D stacked chips where the clock tree and grid are shorted between strata is presented and compared with a DLL-based technique. Both permit at-speed testing of the strata before and after stack assembly. The shorting-based technique is implemented in a 2-strata eDRAM test chip using an IBM 45nm SOI 3D technology. Operation above 2.5GHz is measured.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"48 1","pages":"170-171"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84147863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 0.6V 2.9µW mixed-signal front-end for ECG monitoring 用于心电监护的0.6V 2.9µW混合信号前端
2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-01 DOI: 10.1109/VLSIC.2012.6243792
Marcus Yip, J. Bohorquez, A. Chandrakasan
{"title":"A 0.6V 2.9µW mixed-signal front-end for ECG monitoring","authors":"Marcus Yip, J. Bohorquez, A. Chandrakasan","doi":"10.1109/VLSIC.2012.6243792","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243792","url":null,"abstract":"This paper presents a mixed-signal ECG front-end that uses aggressive voltage scaling to maximize power-efficiency and facilitate integration with low-voltage DSPs. 50/60Hz interference is canceled using mixed-signal feedback, enabling ultra-low-voltage operation by reducing dynamic range requirements. Analog circuits are optimized for ultra-low-voltage, and a SAR ADC with a dual-DAC architecture eliminates the need for a power-hungry ADC buffer. Oversampling and ΔΣ-modulation leveraging near-VT digital processing are used to achieve ultra-low-power operation without sacrificing noise performance and dynamic range. The fully-integrated front-end is implemented in a 0.18μm CMOS process and consumes 2.9μW from 0.6V.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"316 1","pages":"66-67"},"PeriodicalIF":0.0,"publicationDate":"2012-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76502469","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
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