多ghz 3D堆叠芯片的短路全局时钟设计

2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI:10.1109/VLSIC.2012.6243844

L. Pang, P. Restle, M. Wordeman, J. Silberman, R. Franch, G. Maier

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引用次数: 6

摘要

提出了一种时钟树和网格在各层之间缩短的三维堆叠芯片全局时钟分布技术，并与基于dll的技术进行了比较。两者都允许在叠层装配前后对地层进行高速测试。这种基于短路的技术是在采用IBM 45nm SOI 3D技术的2层eDRAM测试芯片中实现的。测量2.5GHz以上的工作频率。

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A shorted global clock design for multi-GHz 3D stacked chips

A global clock distribution technique for 3D stacked chips where the clock tree and grid are shorted between strata is presented and compared with a DLL-based technique. Both permit at-speed testing of the strata before and after stack assembly. The shorting-based technique is implemented in a 2-strata eDRAM test chip using an IBM 45nm SOI 3D technology. Operation above 2.5GHz is measured.

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2012 Symposium on VLSI Circuits (VLSIC)

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