A 22nm dynamically adaptive clock distribution for voltage droop tolerance

2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI:10.1109/VLSIC.2012.6243806

K. Bowman, Carlos Tokunaga, T. Karnik, V. De, J. Tschanz

引用次数: 15

Abstract

A 22nm all-digital dynamically adaptive clock distribution mitigates the impact of high-frequency supply voltage (VCC) droops on microprocessor performance and energy efficiency. Silicon measurements demonstrate simultaneous throughput gains and energy reductions ranging from 14% and 3% at 1.0V to 31% and 15% at 0.6V, respectively, for a 10% VCC droop.

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一种22nm动态自适应时钟分布，用于电压下垂公差

22nm全数字动态自适应时钟分布减轻了高频电源电压(VCC)下降对微处理器性能和能效的影响。硅测量表明，当电压降低10%时，在1.0V时，同时吞吐量提高14%，能耗降低3%，在0.6V时，分别降低31%和15%。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2012 Symposium on VLSI Circuits (VLSIC)

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