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A 1.6-mm2 38-mW 1.5-Gb/s LDPC decoder enabled by refresh-free embedded DRAM 采用免刷新嵌入式DRAM实现的1.6 mm2 38mw 1.5 gb /s LDPC解码器
2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI: 10.1109/VLSIC.2012.6243816
Youn Sung Park, D. Blaauw, D. Sylvester, Zhengya Zhang
{"title":"A 1.6-mm2 38-mW 1.5-Gb/s LDPC decoder enabled by refresh-free embedded DRAM","authors":"Youn Sung Park, D. Blaauw, D. Sylvester, Zhengya Zhang","doi":"10.1109/VLSIC.2012.6243816","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243816","url":null,"abstract":"Memory dominates the power consumption of high-throughput LDPC decoders. A 700 MHz refresh-free embedded DRAM (eDRAM) is designed as a low-power memory to retain data for the required access window. 321-kb eDRAM arrays are integrated in a 1.6 mm2, 65nm LDPC decoder suitable for IEEE 802.11ad. The LDPC decoder consumes 38 mW for a 1.5 Gb/s throughput at 90 MHz and 10 decoding iterations, and it achieves up to 9 Gb/s at 540 MHz.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"32 1","pages":"114-115"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74640723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
A 1.5GHz 1.35mW −112dBc/Hz in-band noise digital phase-locked loop with 50fs/mV supply-noise sensitivity 1.5GHz 1.35mW - 112dBc/Hz带内噪声数字锁相环，电源噪声灵敏度为50fs/mV
2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI: 10.1109/VLSIC.2012.6243853
A. Elshazly, Rajesh Inti, Mrunmay Talegaonkar, P. Hanumolu
{"title":"A 1.5GHz 1.35mW −112dBc/Hz in-band noise digital phase-locked loop with 50fs/mV supply-noise sensitivity","authors":"A. Elshazly, Rajesh Inti, Mrunmay Talegaonkar, P. Hanumolu","doi":"10.1109/VLSIC.2012.6243853","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243853","url":null,"abstract":"A highly digital PLL employs a 1b TDC and a low power regulator to reduce output jitter in the presence of large amount of supply-noise. Fabricated in a 0.13μm CMOS process, the ring-oscillator based DPLL consumes 1.35mW at 1.5GHz output frequency and achieves better than 50fs/mV worst-case noise sensitivity (≡10pspp jitter degradation with 200mVpp noise).","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"274 1","pages":"188-189"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79997258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
1Mb 4T-2MTJ nonvolatile STT-RAM for embedded memories using 32b fine-grained power gating technique with 1.0ns/200ps wake-up/power-off times 1Mb 4T-2MTJ非易失性STT-RAM，用于嵌入式存储器，采用32b细粒度电源门控技术，唤醒/关闭时间为1.0ns/200ps
2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI: 10.1109/VLSIC.2012.6243782
T. Ohsawa, H. Koike, S. Miura, H. Honjo, K. Tokutome, S. Ikeda, T. Hanyu, H. Ohno, T. Endoh
{"title":"1Mb 4T-2MTJ nonvolatile STT-RAM for embedded memories using 32b fine-grained power gating technique with 1.0ns/200ps wake-up/power-off times","authors":"T. Ohsawa, H. Koike, S. Miura, H. Honjo, K. Tokutome, S. Ikeda, T. Hanyu, H. Ohno, T. Endoh","doi":"10.1109/VLSIC.2012.6243782","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243782","url":null,"abstract":"A 1Mb nonvolatile STT-RAM using the 4T-2MTJ cell is designed and fabricated using 90nm CMOS and MTJ processes. 32 cells along a word line (WL) are simultaneously power-gated with quick wake-up/power-off times of 1.0ns/200ps, respectively, to reduce operation power and to eliminate standby power of the chip. The cell is experimentally shown to retain data with static noise margin (SNM) 0.32V under Vdd=1V. The 1Mb chip with 2.19μm2 cell is successfully operated with array access time of 8ns and read power of 10.7mW under 10ns cycle. The macro size of 1Mb STT-RAM is predicted to become smaller than the 1Mb 6T-SRAM in 45nm and beyond.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"25 1","pages":"46-47"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81439381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 57
High area-efficient DC-DC converter using Time-Mode Miller Compensation (TMMC) 基于时模米勒补偿(TMMC)的高效率DC-DC变换器
2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI: 10.1109/VLSIC.2012.6243849
Sung-Wan Hong, Tae-Hwang Kong, Seungchul Jung, Sungwoo Lee, Se-Won Wang, Jong-Pil Im, G. Cho
{"title":"High area-efficient DC-DC converter using Time-Mode Miller Compensation (TMMC)","authors":"Sung-Wan Hong, Tae-Hwang Kong, Seungchul Jung, Sungwoo Lee, Se-Won Wang, Jong-Pil Im, G. Cho","doi":"10.1109/VLSIC.2012.6243849","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243849","url":null,"abstract":"For the controller design of a DC-DC converter, a Time-Mode Miller Compensation (TMMC) is introduced in this paper. Using this concept, the consuming area of the DC-DC converter can be significantly reduced without any off-chip compensation components. The chip is implemented in 0.18μm I/O CMOS whose size is similar to 0.35μm CMOS, and the core size of this work is only 0.12mm2. Peak efficiency is 90.6%, with switching frequency of 1.15MHz.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"46 1","pages":"180-181"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89558766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 5MHz BW 70.7dB SNDR noise-shaped two-step quantizer based ΔΣ ADC 基于5MHz BW 70.7dB SNDR噪声型两步量化器的ΔΣ ADC
2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI: 10.1109/VLSIC.2012.6243840
Taehwan Oh, N. Maghari, U. Moon
{"title":"A 5MHz BW 70.7dB SNDR noise-shaped two-step quantizer based ΔΣ ADC","authors":"Taehwan Oh, N. Maghari, U. Moon","doi":"10.1109/VLSIC.2012.6243840","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243840","url":null,"abstract":"In this paper, a new ΔΣ ADC using a noise-shaped two-step integrating quantizer is presented. Attaining an extra order of noise-shaping from the integrating quantizer, the proposed ΔΣ ADC manifests a second-order noise-shaping with a first-order loop filter. Furthermore, this quantizer provides an 8b quantization in itself, drastically reducing the oversampling requirement. The proposed ADC also incorporates a new feedback DAC topology that alleviates feedback DAC complexity of a two-step 8b quantizer. The measured results of the prototype ADC implemented in a 0.13μm CMOS demonstrate peak SNDR of 70.7dB at 8.1mW power, with an 8x OSR at 80MHz sampling frequency.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"100 1","pages":"162-163"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78227423","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A 100+ meter 12Gb/s/lane copper cable link based on clock-forwarding 基于时钟转发的100+米12Gb/s/lane铜缆链路
2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI: 10.1109/VLSIC.2012.6243813
Tamer A. Ali, Won Ho Park, P. Mulage, Ehung Chen, R. Ho, C. Yang
{"title":"A 100+ meter 12Gb/s/lane copper cable link based on clock-forwarding","authors":"Tamer A. Ali, Won Ho Park, P. Mulage, Ehung Chen, R. Ho, C. Yang","doi":"10.1109/VLSIC.2012.6243813","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243813","url":null,"abstract":"This paper presents a clock-forwarding link architecture for 12Gbps 100+ meters copper cable. The delivery of a low jitter forward clock along the entire cable is enabled by an FIR filtering technique, a low-jitter configurable PLL/MDLL and the proper choice of forwarded frequency Total jitter at the end of the cable is 4.4ps RMS. The data signal is repeated every 8m. The link at each repeater occupies 0.095mm2 of area in a 65nm technology dissipating 48mW.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"122 1","pages":"108-109"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79465284","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 10 MHz BW 50 fJ/conv. continuous time ΔΣ modulator with high-order single opamp integrator using optimization-based design method 10mhz bw50fj /conv。采用基于优化设计方法的高阶单运放积分器的连续时间ΔΣ调制器
2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI: 10.1109/VLSIC.2012.6243839
Kazuo Matsukawa, Koji Obata, Y. Mitani, S. Dosho
{"title":"A 10 MHz BW 50 fJ/conv. continuous time ΔΣ modulator with high-order single opamp integrator using optimization-based design method","authors":"Kazuo Matsukawa, Koji Obata, Y. Mitani, S. Dosho","doi":"10.1109/VLSIC.2012.6243839","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243839","url":null,"abstract":"This paper proposes a new power and area efficient circuit configurations, and also an optimization design method for such configurations. Two types of loopfilters are fabricated, one is a third-order integrator with single opamp for mobile TV-tuners (Modulator A) and the other is a fourth-order (Modulator B) for wide-band mobile receivers. Modulator A and Modulator B are fabricated in 65 nm and 40 nm CMOS processes, respectively. Results show that the new filter with an efficient optimization tool is a very powerful way to develop high efficient ΔΣ.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"8 1","pages":"160-161"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83514468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 36
Components for generating and phase locking 390-GHz signal in 45-nm CMOS 用于在45纳米CMOS中产生和锁相390 ghz信号的组件
2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI: 10.1109/VLSIC.2012.6243764
D. Shim, D. Koukis, D. J. Arenas, D. Tanner, E. Seok, J. Brewer, K. O. Kenneth
{"title":"Components for generating and phase locking 390-GHz signal in 45-nm CMOS","authors":"D. Shim, D. Koukis, D. J. Arenas, D. Tanner, E. Seok, J. Brewer, K. O. Kenneth","doi":"10.1109/VLSIC.2012.6243764","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243764","url":null,"abstract":"Components for generating and phase locking 390-GHz signal are demonstrated using low leakage transistors in 45-nm CMOS. An integrated chain of circuits composed of an 195-GHz oscillator with frequency doubled output at ~390 GHz followed by two cascaded ÷2 injection locked frequency dividers with output frequency of ~49 GHz is demonstrated. The peak power radiated at ~390 GHz by an on-chip antenna is ~2 μW. The oscillator and frequency divider consumes 21 and 6 mW, respectively.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"19 1","pages":"10-11"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82116629","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Nanostructured CMOS wireless ultra-wideband label-free DNA analysis SoC 纳米结构CMOS无线超宽带无标签DNA分析SoC
2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI: 10.1109/VLSIC.2012.6243820
Hamed Mazhab-Jafari, L. Soleymani, K. Abdelhalim, E. Sargent, S. Kelley, R. Genov
{"title":"Nanostructured CMOS wireless ultra-wideband label-free DNA analysis SoC","authors":"Hamed Mazhab-Jafari, L. Soleymani, K. Abdelhalim, E. Sargent, S. Kelley, R. Genov","doi":"10.1109/VLSIC.2012.6243820","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243820","url":null,"abstract":"A 0.13-micron CMOS fully integrated 48-channel UWB label-free DNA analysis SoC is demonstrated in prostate cancer screening. The 3mm×3mm die includes 578 nanostructured DNA sensors, 48 pH sensors, and 48 temperature sensors and reuses key circuits for cyclic voltammetry, amperometry and temperature regulation.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"2 1","pages":"122-123"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76211894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A 61-dB SNDR 700 µm2 second-order all-digital TDC with low-jitter frequency shift oscillators and dynamic flipflops 一个61 db SNDR 700µm2二阶全数字TDC，具有低抖动频移振荡器和动态触发器
2012 Symposium on VLSI Circuits (VLSIC) Pub Date : 2012-06-13 DOI: 10.1109/VLSIC.2012.6243854
T. Konishi, Keisuke Okuno, S. Izumi, M. Yoshimoto, H. Kawaguchi
{"title":"A 61-dB SNDR 700 µm2 second-order all-digital TDC with low-jitter frequency shift oscillators and dynamic flipflops","authors":"T. Konishi, Keisuke Okuno, S. Izumi, M. Yoshimoto, H. Kawaguchi","doi":"10.1109/VLSIC.2012.6243854","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243854","url":null,"abstract":"We present a small-area second-order all-digital time-to-digital converter (TDC) with two frequency shift oscillators (FSOs) comprising inverter chains and dynamic flipflops featuring low jitter. The proposed FSOs can maintain their phase states through continuous oscillation, unlike conventional gated ring oscillators (GROs) that are affected by transistor leakage. Our proposed FSOTDC is more robust and is eligible for all-digital TDC architectures in recent leaky processes. Low-jitter dynamic flipflops are adopted as a quantization noise propagator (QNP). A frequency mismatch occurring between the two FSOs can be canceled out using a least mean squares (LMS) filter so that second-order noise shaping is possible. In a standard 65-nm CMOS process, an SNDR of 61 dB is achievable at an input bandwidth of 500 kHz and a sampling rate of 16 MHz, where the respective area and power are 700 μm2 and 281 μW.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":"108 1","pages":"190-191"},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78780563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
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