Tamer A. Ali, Won Ho Park, P. Mulage, Ehung Chen, R. Ho, C. Yang
{"title":"基于时钟转发的100+米12Gb/s/lane铜缆链路","authors":"Tamer A. Ali, Won Ho Park, P. Mulage, Ehung Chen, R. Ho, C. Yang","doi":"10.1109/VLSIC.2012.6243813","DOIUrl":null,"url":null,"abstract":"This paper presents a clock-forwarding link architecture for 12Gbps 100+ meters copper cable. The delivery of a low jitter forward clock along the entire cable is enabled by an FIR filtering technique, a low-jitter configurable PLL/MDLL and the proper choice of forwarded frequency Total jitter at the end of the cable is 4.4ps RMS. The data signal is repeated every 8m. The link at each repeater occupies 0.095mm2 of area in a 65nm technology dissipating 48mW.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A 100+ meter 12Gb/s/lane copper cable link based on clock-forwarding\",\"authors\":\"Tamer A. Ali, Won Ho Park, P. Mulage, Ehung Chen, R. Ho, C. Yang\",\"doi\":\"10.1109/VLSIC.2012.6243813\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a clock-forwarding link architecture for 12Gbps 100+ meters copper cable. The delivery of a low jitter forward clock along the entire cable is enabled by an FIR filtering technique, a low-jitter configurable PLL/MDLL and the proper choice of forwarded frequency Total jitter at the end of the cable is 4.4ps RMS. The data signal is repeated every 8m. The link at each repeater occupies 0.095mm2 of area in a 65nm technology dissipating 48mW.\",\"PeriodicalId\":6347,\"journal\":{\"name\":\"2012 Symposium on VLSI Circuits (VLSIC)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-06-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2012 Symposium on VLSI Circuits (VLSIC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.2012.6243813\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 Symposium on VLSI Circuits (VLSIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2012.6243813","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 100+ meter 12Gb/s/lane copper cable link based on clock-forwarding
This paper presents a clock-forwarding link architecture for 12Gbps 100+ meters copper cable. The delivery of a low jitter forward clock along the entire cable is enabled by an FIR filtering technique, a low-jitter configurable PLL/MDLL and the proper choice of forwarded frequency Total jitter at the end of the cable is 4.4ps RMS. The data signal is repeated every 8m. The link at each repeater occupies 0.095mm2 of area in a 65nm technology dissipating 48mW.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
