A. Elshazly, Rajesh Inti, Mrunmay Talegaonkar, P. Hanumolu
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A 1.5GHz 1.35mW −112dBc/Hz in-band noise digital phase-locked loop with 50fs/mV supply-noise sensitivity
A highly digital PLL employs a 1b TDC and a low power regulator to reduce output jitter in the presence of large amount of supply-noise. Fabricated in a 0.13μm CMOS process, the ring-oscillator based DPLL consumes 1.35mW at 1.5GHz output frequency and achieves better than 50fs/mV worst-case noise sensitivity (≡10pspp jitter degradation with 200mVpp noise).
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